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[134.60.170.20]) by smtp.gmail.com with ESMTPSA id y191-v6sm1670873wmy.4.2018.07.31.02.23.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 31 Jul 2018 02:23:00 -0700 (PDT) From: Philipp Rossak To: mchehab@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, sean@mess.org, p.zabel@pengutronix.de, andi.shyti@samsung.com Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Subject: [PATCH v6 1/4] ARM: dts: sun8i: a83t: Add the cir pin for the A83T Date: Tue, 31 Jul 2018 11:22:55 +0200 Message-Id: <20180731092258.2279-2-embed3d@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180731092258.2279-1-embed3d@gmail.com> References: <20180731092258.2279-1-embed3d@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The CIR Pin of the A83T is located at PL12. Signed-off-by: Philipp Rossak --- arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 2be23d600957..afed6c0dea6f 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -1004,6 +1004,11 @@ interrupt-controller; #interrupt-cells = <3>; + r_cir_pin: r-cir-pin { + pins = "PL12"; + function = "s_cir_rx"; + }; + r_rsb_pins: r-rsb-pins { pins = "PL0", "PL1"; function = "s_rsb"; -- 2.11.0