Received: by 2002:ac0:a5a7:0:0:0:0:0 with SMTP id m36-v6csp4942737imm; Tue, 31 Jul 2018 02:52:28 -0700 (PDT) X-Google-Smtp-Source: AAOMgpcSz2QSUNLNeRiulxW0Qi9zydjYxGnCelodZnkO30aA5tuTTW/ejwX4+2PHC76srzZn2szw X-Received: by 2002:a62:4ece:: with SMTP id c197-v6mr21767632pfb.240.1533030748305; Tue, 31 Jul 2018 02:52:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533030748; cv=none; d=google.com; s=arc-20160816; b=ks37wBr6bZSpIEQql+BIPoja0DoG1wvt22k9sN5bwxyDr0nye3kpO/40AmMlaJ7g/A 495rcMboweAqdyekpDuwqf9OocZyf9DaGpCDfiQgaNQGlpj9YbQiyz6yjuS/a6QPsKdc FUI26I/b20UnfAhYq3Lq27qS3cuu2xps5gEmrbXmCOUpePe9ruU0KlEZWXaNdTLremdc abeCBJqf0sQpeq1onfc+qrMN7+VMkKrjSJvQeasOHaLag65UiQDSCDrhmikZUHeRzvBB yh7i0IjwuK10F6s3opcEj9JLsSKhUHufwWRWJCfo9N4fzvkDgVMrZUWLPn1RDxt4o8D+ P0wA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :references:in-reply-to:date:cc:to:from:subject:message-id :arc-authentication-results; bh=KQEUncTAR0rfBJgu0478F8kShKl1giQlBAwrKzlifXM=; b=A8FhUg3WcS1gQ71OeukDnVn9XT31wv8a6o/kqpuyxHijxZgShQJYIo1DVtFv1N+ou7 1cPmc/HHKJm6tsuh/cMssiUTlEDFrSex5kzYYDE3UvQLlPYY+QYWrwQJGFv0enJkebqj Y4HiRNIgeqrvclg195AKt+QBxvSj29TWMBrRbHKGjUWPpMTpz8h211QFPFUIFHrHGO1l MlAuKsxQ9Tv3pq1fIYnmy9OvA21Hw3804De4d3+WQRLsMOL2a52gDEgfAyb9XLBr+Tyo TqDy9XlPby+6FqS3KY7kdhMUgvez4IlpwS9NWUw6dtmplYW9Bjo24nX8qMT7NH5s6XeY pmNw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w3-v6si11916301pgp.220.2018.07.31.02.52.12; Tue, 31 Jul 2018 02:52:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731311AbeGaLay (ORCPT + 99 others); Tue, 31 Jul 2018 07:30:54 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:47975 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729784AbeGaLax (ORCPT ); Tue, 31 Jul 2018 07:30:53 -0400 X-UUID: 0d6b2ce08f8f4b6baf6ec83b2c2a6b41-20180731 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1010374874; Tue, 31 Jul 2018 17:51:16 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Tue, 31 Jul 2018 17:51:14 +0800 Received: from [172.21.77.33] (172.21.77.33) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Tue, 31 Jul 2018 17:51:14 +0800 Message-ID: <1533030674.13386.7.camel@mtkswgap22> Subject: RE: Re: [PATCH v1 1/2] arm64: dts: mt7622: add some misc device nodes From: Ryder Lee To: Matthias Brugger CC: Rob Herring , Sean Wang , , , , Date: Tue, 31 Jul 2018 17:51:14 +0800 In-Reply-To: <1533026633.10540.20.camel@mtkswgap22> References: <2ff39c40ef6bc3054667e63c785a1d28527b5ddf.1531753039.git.ryder.lee@mediatek.com> <864955d5-26c4-a5f3-ec1a-420acba50880@gmail.com> <2839886f07dc47afb9a05d06fb1acc84@mtkmbs08n1.mediatek.inc> <1533026633.10540.20.camel@mtkswgap22> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3-0ubuntu6 Content-Transfer-Encoding: 8bit MIME-Version: 1.0 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 2018-07-31 at 16:43 +0800, Ryder Lee wrote: > Hi Matthias, > > Sorry for the late reply. > > On Tue, 2018-07-31 at 16:17 +0800, Ryder Lee (李庚諺) wrote: > > Hi Ryder, > > > > On 16/07/18 16:59, Ryder Lee wrote: > > > Add some misc nodes support - timer and ARM CCI-400. > > > > > > Signed-off-by: Ryder Lee > > > --- > > > arch/arm64/boot/dts/mediatek/mt7622.dtsi | 36 > > > ++++++++++++++++++++++++++++++++ > > > 1 file changed, 36 insertions(+) > > > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi > > > b/arch/arm64/boot/dts/mediatek/mt7622.dtsi > > > index 9213c96..8cdec52 100644 > > > --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi > > > +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi > > > @@ -217,6 +217,16 @@ > > > #reset-cells = <1>; > > > }; > > > > > > + timer: timer@10004000 { > > > + compatible = "mediatek,mt7622-timer", > > > + "mediatek,mt6577-timer"; > > > + reg = <0 0x10004000 0 0x80>; > > > + interrupts = ; > > > + clocks = <&infracfg CLK_INFRA_APXGPT_PD>, > > > + <&topckgen CLK_TOP_RTC>; > > > + clock-names = "system-clk", "rtc-clk"; > > > + }; > > > + > > > scpsys: scpsys@10006000 { > > > compatible = "mediatek,mt7622-scpsys", > > > "syscon"; > > > @@ -317,6 +327,32 @@ > > > <0 0x10360000 0 0x2000>; > > > }; > > > > > > + cci: cci@10390000 { > > > + compatible = "arm,cci-400"; > > > + #address-cells = <1>; > > > + #size-cells = <1>; > > > + reg = <0 0x10390000 0 0x1000>; > > > + ranges = <0 0 0x10390000 0x10000>; > > > > From my understanding of the binding description ranges should hold child address, parent address and size of the region in the child address space. I can see in arch/arm64 two different variants using 4 ranges values (like here) and using three values. > > > > @Rob + Will what is the preferred way to describe this? > > Hmmm... it's just a copy-paste (I take zynqmp.dtsi as an example). > > > + > > > + cci_control0: slave-if@1000 { > > > + compatible = "arm,cci-400-ctrl-if"; > > > + interface-type = "ace-lite"; > > > + reg = <0x1000 0x1000>; > > > + }; > > > > Don't we need to add phandles to the cci-control-port property in the cpu nodes? I forgot to answer this question in previous mail. Yes, we need it. I will add the cci-control-port property in the cpu nodes and add the child node PMU in cci-400 - somehow I forgot to add them. Thanks for your reminder. > > Regards, > > Matthias > > MT7622 use cci-400 to improve performance (DMA IO coherence) for > high-speed IPs. (i.e., ETH/WIFI/SATA/...) > > I added it early but actually the related features have not supported in > mainline yet. > > Ryder