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[209.132.180.67]) by mx.google.com with ESMTP id g87-v6si18215869pfg.225.2018.08.01.09.34.05; Wed, 01 Aug 2018 09:34:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390338AbeHASTd (ORCPT + 99 others); Wed, 1 Aug 2018 14:19:33 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:2973 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390069AbeHASTc (ORCPT ); Wed, 1 Aug 2018 14:19:32 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1, AES128-SHA) id ; Wed, 01 Aug 2018 09:32:48 -0700 Received: from HQMAIL103.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Wed, 01 Aug 2018 09:33:00 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Wed, 01 Aug 2018 09:33:00 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 1 Aug 2018 16:32:59 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Wed, 1 Aug 2018 16:32:59 +0000 Received: from dhcp-10-21-25-168.Nvidia.com (Not Verified[10.21.25.201]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Wed, 01 Aug 2018 09:32:59 -0700 From: Aapo Vienamo To: Rob Herring , Mark Rutland , Thierry Reding , Jonathan Hunter , Ulf Hansson , Adrian Hunter , Mikko Perttunen , Stefan Agner CC: , , , , Aapo Vienamo Subject: [PATCH 06/40] soc/tegra: pmc: Factor out DPD register bit calculation Date: Wed, 1 Aug 2018 19:31:56 +0300 Message-ID: <1533141150-10511-7-git-send-email-avienamo@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533141150-10511-1-git-send-email-avienamo@nvidia.com> References: <1533141150-10511-1-git-send-email-avienamo@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Factor out the the code to calculate the correct DPD register and bit number for a given pad. This logic will be needed to query the status register. Signed-off-by: Aapo Vienamo Acked-by: Jon Hunter --- drivers/soc/tegra/pmc.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index f926332..393ca72 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -922,11 +922,12 @@ tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id) return NULL; } -static int tegra_io_pad_prepare(enum tegra_io_pad id, unsigned long *request, - unsigned long *status, u32 *mask) +static int tegra_io_pad_get_dpd_register_bit(enum tegra_io_pad id, + unsigned long *request, + unsigned long *status, + u32 *mask) { const struct tegra_io_pad_soc *pad; - unsigned long rate, value; pad = tegra_io_pad_find(pmc, id); if (!pad) { @@ -947,6 +948,19 @@ static int tegra_io_pad_prepare(enum tegra_io_pad id, unsigned long *request, *request = pmc->soc->regs->dpd2_req; } + return 0; +} + +static int tegra_io_pad_prepare(enum tegra_io_pad id, unsigned long *request, + unsigned long *status, u32 *mask) +{ + unsigned long rate, value; + int err; + + err = tegra_io_pad_get_dpd_register_bit(id, request, status, mask); + if (err) + return err; + if (pmc->clk) { rate = clk_get_rate(pmc->clk); if (!rate) { -- 2.7.4