Received: by 2002:ac0:a5a7:0:0:0:0:0 with SMTP id m36-v6csp1063114imm; Wed, 1 Aug 2018 09:35:28 -0700 (PDT) X-Google-Smtp-Source: AAOMgpccPrryPutFFg3kS6XhwgQ5qqY6+rIRaQ6y1rwy3VljCNj4jOud6QrfkNXr67QsqzcwWEWY X-Received: by 2002:a63:1a49:: with SMTP id a9-v6mr25977329pgm.423.1533141328533; Wed, 01 Aug 2018 09:35:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533141328; cv=none; d=google.com; s=arc-20160816; b=cVwGTQiHr1CsVQFZuEgEAYswX6878dl0uAfUwScOdgxw48jb3iU+ECSTO8KARvVtAY dddJhoIcOsjD7TX1carLSQl1ddRATKOJ6a55r7+uNf2L2H11gTdBorrGifxa/OiKuvzJ Ea7c/NX61OIqN4R4AyBJeMfP+VqjVq/lUD6ykXgqYuN/LGOiyhtSF0tGrLNjVFgOzelZ eHEfFKsx24zhOihl0Ge+CuhnqkfMavvJ70/qXvhd0BBAhP/VM3px+bx24K7i5aqRNf2W B+jaAwR6WxQTnG3R0iz5dzFTEW9g4D+SGnE3r2Bk4bxoDayltn/AJawPIvUOKeTs9oVF rmiA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=REtpcvW3LWs2Mih6SqMDalYgZ+IS3Z6tFXWRXBpwsg4=; b=C3pN1Xc6No//ru/lhr3DpKGMRM2C5YK+cJt57eiE839YAAmBfkIBGStMTqK29+8Q6n icIhicZL/nN6j6fimtAtH4FFq7iFR9X0DnemRCvHw0p+ePKz7ZuhZKVWxOFmFhPcb7Uf 52ptNtHrgyaGNq07jiI02agQA7L5Oa5mVuu+VL+b9f1ZD8gORDdJ77dA6duo74yA3gzv C8I5EYWoyuiK3C0rDWpJJP3eaVi1pgCiue1LaifGJ3Xj/Dptt1fJs3VgvUUOAFnpzOjJ cimTb32CkOomVDl14EXxLCfh7uvuNvfB39HSnqtjWXZbxkuGlRMGCy7j0mqq87uPsX3Y qpKA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z12-v6si14361681pgu.692.2018.08.01.09.35.13; Wed, 01 Aug 2018 09:35:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390460AbeHASTz (ORCPT + 99 others); Wed, 1 Aug 2018 14:19:55 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:2467 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390395AbeHASTy (ORCPT ); Wed, 1 Aug 2018 14:19:54 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1, AES128-SHA) id ; Wed, 01 Aug 2018 09:33:16 -0700 Received: from HQMAIL104.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 01 Aug 2018 09:33:21 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 01 Aug 2018 09:33:21 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 1 Aug 2018 16:33:21 +0000 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 1 Aug 2018 16:33:21 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Wed, 1 Aug 2018 16:33:21 +0000 Received: from dhcp-10-21-25-168.Nvidia.com (Not Verified[10.21.25.201]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Wed, 01 Aug 2018 09:33:20 -0700 From: Aapo Vienamo To: Rob Herring , Mark Rutland , Thierry Reding , Jonathan Hunter , Ulf Hansson , Adrian Hunter , Mikko Perttunen , "Stefan Agner" CC: , , , , Aapo Vienamo Subject: [PATCH 13/40] mmc: tegra: Poll for calibration completion Date: Wed, 1 Aug 2018 19:32:03 +0300 Message-ID: <1533141150-10511-14-git-send-email-avienamo@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533141150-10511-1-git-send-email-avienamo@nvidia.com> References: <1533141150-10511-1-git-send-email-avienamo@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Implement polling with 10 ms timeout for automatic pad drive strength calibration. Signed-off-by: Aapo Vienamo --- drivers/mmc/host/sdhci-tegra.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 7d98455..c8ff267 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -50,6 +51,9 @@ #define SDHCI_AUTO_CAL_START BIT(31) #define SDHCI_AUTO_CAL_ENABLE BIT(29) +#define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec +#define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31) + #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) @@ -228,13 +232,20 @@ static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) { - u32 val; + u32 reg; + int ret; + + reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); + reg |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START; + sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); - mdelay(1); + /* 10 ms timeout */ + ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS, + reg, !(reg & SDHCI_TEGRA_AUTO_CAL_ACTIVE), + 1, 10000); - val = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); - val |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START; - sdhci_writel(host,val, SDHCI_TEGRA_AUTO_CAL_CONFIG); + if (ret) + dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); } static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) -- 2.7.4