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[209.132.180.67]) by mx.google.com with ESMTP id h14-v6si15784538pgg.540.2018.08.01.09.37.34; Wed, 01 Aug 2018 09:37:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390513AbeHASUE (ORCPT + 99 others); Wed, 1 Aug 2018 14:20:04 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:4324 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390465AbeHASUD (ORCPT ); Wed, 1 Aug 2018 14:20:03 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1, AES128-SHA) id ; Wed, 01 Aug 2018 09:33:18 -0700 Received: from HQMAIL104.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 01 Aug 2018 09:33:31 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 01 Aug 2018 09:33:31 -0700 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 1 Aug 2018 16:33:30 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Wed, 1 Aug 2018 16:33:30 +0000 Received: from dhcp-10-21-25-168.Nvidia.com (Not Verified[10.21.25.201]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Wed, 01 Aug 2018 09:33:30 -0700 From: Aapo Vienamo To: Rob Herring , Mark Rutland , Thierry Reding , Jonathan Hunter , Ulf Hansson , Adrian Hunter , Mikko Perttunen , Stefan Agner CC: , , , , Aapo Vienamo Subject: [PATCH 16/40] mmc: tegra: Disable card clock during pad calibration Date: Wed, 1 Aug 2018 19:32:06 +0300 Message-ID: <1533141150-10511-17-git-send-email-avienamo@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533141150-10511-1-git-send-email-avienamo@nvidia.com> References: <1533141150-10511-1-git-send-email-avienamo@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Disable the card clock during automatic pad drive strength calibration and re-enable it afterwards. Signed-off-by: Aapo Vienamo --- drivers/mmc/host/sdhci-tegra.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 9e22fec..c2b388b 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -260,11 +260,35 @@ static void tegra_sdhci_configure_cal_pad(struct sdhci_host *host, bool enable) } } +static bool tegra_sdhci_configure_card_clk(struct sdhci_host *host, bool enable) +{ + bool orig_enabled; + u32 reg; + + reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + orig_enabled = !!(reg & SDHCI_CLOCK_CARD_EN); + + if (orig_enabled == enable) + return orig_enabled; + + if (enable) + reg |= SDHCI_CLOCK_CARD_EN; + else + reg &= ~SDHCI_CLOCK_CARD_EN; + + sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); + + return orig_enabled; +} + static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) { + bool card_clk_enabled; u32 reg; int ret; + card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); + tegra_sdhci_configure_cal_pad(host, true); reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); @@ -278,6 +302,8 @@ static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) tegra_sdhci_configure_cal_pad(host, false); + tegra_sdhci_configure_card_clk(host, card_clk_enabled); + if (ret) dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); } -- 2.7.4