Received: by 2002:ac0:a5a7:0:0:0:0:0 with SMTP id m36-v6csp1065795imm;
        Wed, 1 Aug 2018 09:38:06 -0700 (PDT)
X-Google-Smtp-Source: AAOMgpfy+n5cyc2b2ShgcO7mihJOvD6vBSPm1onidj4sTLIaOqcy3mm2InhnqE1vIPv8c+9jBD/x
X-Received: by 2002:a17:902:280b:: with SMTP id e11-v6mr25311148plb.298.1533141486042;
        Wed, 01 Aug 2018 09:38:06 -0700 (PDT)
ARC-Seal: i=1; a=rsa-sha256; t=1533141486; cv=none;
        d=google.com; s=arc-20160816;
        b=t9zKMDthdVvYvRwm9B9xFPFukqdU24D7X8MxI9gaVIwJ9LwJMWyOzJTwpEu0GF3a1a
         Nrrx3PKu7QK78MXF8JUqt7IAgQQuw+nl3bW0jdlA8NsiT+PABv7WHg72w8I9vEY0dvH+
         IjiT6q02c3aDM9e0jS3P80UTgkQ6uoKmuq0Z0Fnwl2fYIaVhkwsOb+Y2uH+XseOAw+yW
         a8nPeQB1F9aypFXydJyk0+ckNziNHoeUJhqjrv1q86KypQyEuOJcclJbfmx1II7yhqWs
         xTp26UVBx0eFpLYXTZ7XpejNhW0fQqc0C4D/6lgH39jBBq0ERukfR3ljtLmUZDYgoXET
         rR4A==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816;
        h=list-id:precedence:sender:mime-version:references:in-reply-to
         :message-id:date:subject:cc:to:from:arc-authentication-results;
        bh=uBbMZ0NS5H/zvN2wOwfdhvbla5U1fVcz8esvNjQmolE=;
        b=iCU3h6KO8OpQoJksvNoIR10AhFUpuHDOsVcUYErkIAdwavXWxI47kzn/sIE34z8Eip
         xM2YcfWpMtgRzfLc2GBR8s09nYGKf4DR4zXqmI623CLBx3WBqlWigvWODDejrYADCE5s
         Z6fD9PQRUET8YBdEBcNM4ZGCqwB7+QqehjvdnY9POTSE4NtMzIefXjpvDO9JSkbGp8kp
         Lp7lVVywlIffr3KHj+hhxTnjSXTHLgjECzCkagC03RBYY7FrHF7PW9PabyuXsK86FLlq
         yoFbmmg6VRHVfGR2/snCYXvLcdN9dcH+EuBQkpai3DlIXs+X2f9RJJ4dH/oOOTJBM6Zh
         qDfQ==
ARC-Authentication-Results: i=1; mx.google.com;
       spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org;
       dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com
Return-Path: <linux-kernel-owner@vger.kernel.org>
Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67])
        by mx.google.com with ESMTP id m32-v6si15562256pgl.622.2018.08.01.09.37.51;
        Wed, 01 Aug 2018 09:38:06 -0700 (PDT)
Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
Authentication-Results: mx.google.com;
       spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org;
       dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
        id S2403918AbeHASUo (ORCPT <rfc822;krseo358@gmail.com> + 99 others);
        Wed, 1 Aug 2018 14:20:44 -0400
Received: from hqemgate15.nvidia.com ([216.228.121.64]:3093 "EHLO
        hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org
        with ESMTP id S2403846AbeHASUm (ORCPT
        <rfc822;linux-kernel@vger.kernel.org>);
        Wed, 1 Aug 2018 14:20:42 -0400
Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1, AES128-SHA)
        id <B5b61e0fd0002>; Wed, 01 Aug 2018 09:34:05 -0700
Received: from HQMAIL101.nvidia.com ([172.20.161.6])
  by hqpgpgate101.nvidia.com (PGP Universal service);
  Wed, 01 Aug 2018 09:34:10 -0700
X-PGP-Universal: processed;
        by hqpgpgate101.nvidia.com on Wed, 01 Aug 2018 09:34:10 -0700
Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL101.nvidia.com
 (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 1 Aug
 2018 16:34:10 +0000
Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com
 (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend
 Transport; Wed, 1 Aug 2018 16:34:10 +0000
Received: from dhcp-10-21-25-168.Nvidia.com (Not Verified[10.21.25.201]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121)
        id <B5b61e0ff0000>; Wed, 01 Aug 2018 09:34:09 -0700
From:   Aapo Vienamo <avienamo@nvidia.com>
To:     Rob Herring <robh+dt@kernel.org>,
        Mark Rutland <mark.rutland@arm.com>,
        Thierry Reding <thierry.reding@gmail.com>,
        Jonathan Hunter <jonathanh@nvidia.com>,
        Ulf Hansson <ulf.hansson@linaro.org>,
        Adrian Hunter <adrian.hunter@intel.com>,
        Mikko Perttunen <mperttunen@nvidia.com>,
        Stefan Agner <stefan@agner.ch>
CC:     <devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, <linux-mmc@vger.kernel.org>,
        Aapo Vienamo <avienamo@nvidia.com>
Subject: [PATCH 29/40] mmc: tegra: Enable UHS and HS200 modes for Tegra186
Date:   Wed, 1 Aug 2018 19:32:19 +0300
Message-ID: <1533141150-10511-30-git-send-email-avienamo@nvidia.com>
X-Mailer: git-send-email 2.7.4
In-Reply-To: <1533141150-10511-1-git-send-email-avienamo@nvidia.com>
References: <1533141150-10511-1-git-send-email-avienamo@nvidia.com>
X-NVConfidentiality: public
MIME-Version: 1.0
Content-Type: text/plain
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

Set nvquirks to enable higher speed modes.

Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
---
 drivers/mmc/host/sdhci-tegra.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 03a6bf7..7f1ac4a 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -872,7 +872,9 @@ static const struct sdhci_tegra_soc_data soc_data_tegra186 = {
 	.pdata = &sdhci_tegra186_pdata,
 	.nvquirks = NVQUIRK_NEEDS_PAD_CONTROL |
 		    NVQUIRK_HAS_PADCALIB |
-		    NVQUIRK_DIS_CARD_CLK_CONFIG_TAP,
+		    NVQUIRK_DIS_CARD_CLK_CONFIG_TAP |
+		    NVQUIRK_ENABLE_SDR50 |
+		    NVQUIRK_ENABLE_SDR104,
 };
 
 static const struct of_device_id sdhci_tegra_dt_match[] = {
-- 
2.7.4