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[209.132.180.67]) by mx.google.com with ESMTP id k38-v6si11399648pgi.147.2018.08.01.13.05.04; Wed, 01 Aug 2018 13:05:19 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=nO3qBraU; dkim=pass header.i=@codeaurora.org header.s=default header.b=H4KXFraH; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731482AbeHAVve (ORCPT + 99 others); Wed, 1 Aug 2018 17:51:34 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:36294 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727252AbeHAVvd (ORCPT ); Wed, 1 Aug 2018 17:51:33 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 195B360275; Wed, 1 Aug 2018 20:04:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1533153847; bh=AycGWAS9RfsyqyoQJcC6qknLtu6knsJAxQ3hmDs39o4=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=nO3qBraUgWsVYI5CAmIw6BCvIanrwpAyfVVNlI6nX/dDqWXv5H22UH1GqIEdpIg1U s4TGd8mPhQaGnBQwMekh+FmfmKBLiE+U3JZRoC1NMcx8B5eh2vN8+XBVSXJ4arr2cE QWx/xuAtwWE0C3mQi9aaXs9YOy8ybG/VcJ5zF0mE= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from localhost (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 3B57E60264; Wed, 1 Aug 2018 20:04:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1533153846; bh=AycGWAS9RfsyqyoQJcC6qknLtu6knsJAxQ3hmDs39o4=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=H4KXFraHQ4RDa8Sa62xu7lIqLuXPPuNGlaEcuWQP9Bm6C4NB2OlnzcqR6LTeCRSf7 LiehGn5uzhWhMdIiYmlSZI6LWfw8uffIuBGoLAd4MUU5Ew2hbFBTIHiIKM6glRJTM7 CaH477ySmsH/Q5DtIJ+EG6TxAhnXd7xIO8iKCq5g= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 3B57E60264 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org Date: Wed, 1 Aug 2018 14:04:05 -0600 From: Lina Iyer To: Marc Zyngier Cc: swboyd@chromium.org, evgreen@chromium.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, rplsssn@codeaurora.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, rnayak@codeaurora.org, devicetree@vger.kernel.org Subject: Re: [PATCH RESEND RFC 2/4] drivers: pinctrl: qcom: add wakeup gpio map for sdm845 Message-ID: <20180801200405.GB6422@codeaurora.org> References: <20180801020021.9782-1-ilina@codeaurora.org> <20180801020021.9782-3-ilina@codeaurora.org> <8636vyxyub.wl-marc.zyngier@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline In-Reply-To: <8636vyxyub.wl-marc.zyngier@arm.com> User-Agent: Mutt/1.10.0 (2018-05-17) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Aug 01 2018 at 02:42 -0600, Marc Zyngier wrote: >On Wed, 01 Aug 2018 03:00:19 +0100, >Lina Iyer wrote: >> >> Add GPIO to PDC pin map for the SDM845 SoC. >> >> Signed-off-by: Lina Iyer >> --- >> drivers/pinctrl/qcom/pinctrl-sdm845.c | 76 +++++++++++++++++++++++++++ >> 1 file changed, 76 insertions(+) >> >> diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c >> index 2ab7a8885757..e93660922dc2 100644 >> --- a/drivers/pinctrl/qcom/pinctrl-sdm845.c >> +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c >> @@ -1277,6 +1277,80 @@ static const struct msm_pingroup sdm845_groups[] = { >> UFS_RESET(ufs_reset, 0x99f000), >> }; >> >> +static struct msm_pinctrl_pdc_map sdm845_wakeup_gpios[] = { > >[huge array] > >> +}; > >Why isn't that array part of the DT? I'd expect other SoCs to >eventually use a similar mechanism, no? > I agree and it should be. One place I am thinking is to add it to the DT definition of PDC controller as a data argument - tlmm: pinctrl@000000{ [...] interrupts-extended = <&pdc 30 IRQ_TYPE_LEVEL_HIGH 1>, <&pdc 31 IRQ_TYPE_LEVEL_HIGH 3>, <&pdc 32 IRQ_TYPE_LEVEL_HIGH 5>, ^ |--- Provide the GPIO for the PDC pin here. }; pdc: interrupt-controller@b220000 { compatible = "qcom,sdm845-pdc"; reg = <0xb220000 0x30000>; qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>; #interrupt-cells = <3>; <-------- Increase this from 2 ? interrupt-parent = <&intc>; interrupt-controller; }; Would that be acceptable? Thanks, Lina