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In-Reply-To: <mhng-38cc8366-10dd-4ea1-993f-bd453640aa66@palmer-si-x1c4>
From:   Zong Li <zongbox@gmail.com>
Date:   Thu, 2 Aug 2018 09:26:48 +0800
Message-ID: <CA+ZOyag=bAB6p_mah+g2DzffsABV3uig0qxMvTWZjunYAtrfkg@mail.gmail.com>
Subject: Re: [PATCH] RISC-V: Add the directive for alignment of stvec's value
To:     Palmer Dabbelt <palmer@sifive.com>
Cc:     Zong Li <zong@andestech.com>, linux-riscv@lists.infradead.org,
        aou@eecs.berkeley.edu,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        greentime@adnestech.com
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Palmer Dabbelt <palmer@sifive.com> =E6=96=BC 2018=E5=B9=B48=E6=9C=882=E6=97=
=A5 =E9=80=B1=E5=9B=9B =E4=B8=8A=E5=8D=888:38=E5=AF=AB=E9=81=93=EF=BC=9A
>
> On Wed, 20 Jun 2018 18:40:07 PDT (-0700), zong@andestech.com wrote:
> > The stvec's value must be 4 byte alignment by specification definition.
> > This directive avoids to stvec be set the non-alignment value by the
> > following code in head.S
> >
> >  /* Point stvec to virtual address of intruction after satp write */
> > la a0, 1f
> > add a0, a0, a1
> > csrw stvec, a0
> >
> > Signed-off-by: Zong Li <zong@andestech.com>
> > ---
> >  arch/riscv/kernel/head.S | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> > index 396ec7b349ce..ae7b204f531c 100644
> > --- a/arch/riscv/kernel/head.S
> > +++ b/arch/riscv/kernel/head.S
> > @@ -94,6 +94,7 @@ relocate:
> >       or a0, a0, a1
> >       sfence.vma
> >       csrw sptbr, a0
> > +.align 2
> >  1:
> >       /* Set trap vector to spin forever to help debug */
> >       la a0, .Lsecondary_park
>
> I don't think this is actually correct: you shouldn't be aligning the add=
ress
> at which stvec is set, but the address that stvec is set to.  If this is =
fixing
> anything then it's probably just by coincidence as it's causing
> .Lsecondary_park to be aligned.
>
> I think this patch is the correct fix
>
>     diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
>     index 6e07ed37bbff..d1beecf1d060 100644
>     --- a/arch/riscv/kernel/head.S
>     +++ b/arch/riscv/kernel/head.S
>     @@ -143,6 +143,7 @@ relocate:
>         tail smp_callin
>      #endif
>
>     +.align 2
>      .Lsecondary_park:
>         /* We lack SMP support or have too many harts, so park this hart =
*/
>         wfi
>
> Thanks for pointing this out!
>
The position which I set in this patch is also be set to stvec for jumping =
to
correct VA at satp enabling. The label .Lsecondary_park is also be set to s=
tvec,
I don't notice it because as you said, this label address is correct
just by coincidence.
I think there are two places need to be aligned.

The first setting as following:
relocate:
        ...
        /* Point stvec to virtual address of intruction after satp write */
        la a0, 1f
        add a0, a0, a1
        csrw stvec, a0    <-----------  first set
        ...
        sfence.vma
        csrw sptbr, a0
1:
        /* Set trap vector to spin forever to help debug */
        la a0, .Lsecondary_park
        csrw stvec, a0