Received: by 2002:ac0:a5a7:0:0:0:0:0 with SMTP id m36-v6csp2129048imm;
        Thu, 2 Aug 2018 06:44:55 -0700 (PDT)
X-Google-Smtp-Source: AAOMgpeNOoUBEqdGLfXL8XBW2TktJZ78rSrcQabnsFOiBE41MJXDKdVKy1ikOfrZL+2lXbPviP7s
X-Received: by 2002:a62:a018:: with SMTP id r24-v6mr3116223pfe.144.1533217495006;
        Thu, 02 Aug 2018 06:44:55 -0700 (PDT)
ARC-Seal: i=1; a=rsa-sha256; t=1533217494; cv=none;
        d=google.com; s=arc-20160816;
        b=kfX9bXUHDwpiQmzXfiAvYn6iREzuysO6nNxTmd979I+OJkaj7gDC3fXTsTR0QsIebL
         PaxdxbjPpaEGchKfryKDXIcl88AazhLK8+xVIjDccgUnFqrL8MVvOtKeoJ0l3JZFVVwM
         l+7pbnDDrgonBrnsn3cgmi7fHcm7dLWZ5R+IYYtijpNOoDnxF+BQYfY1s0bTecnWB/HO
         lkczvK7r3X2M1BroGuUmHkL1t8+AlL6rk9J0IxcwjjNuogidNHEWbH+uWc6e1hdrXBlz
         mDYXvsLt02K7fw+L3F1CiV2BS96bqimVg2uscPzc7Xy0Arj6vnctlT5aMrj4nA8uiQ5f
         0mJQ==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816;
        h=list-id:precedence:sender:content-transfer-encoding
         :content-language:in-reply-to:mime-version:user-agent:date
         :message-id:from:references:cc:to:subject:arc-authentication-results;
        bh=M4FeDT8QHYeYZQUMiW8n0kpcNYSBcEz5ntmxeeDef4M=;
        b=SaFk2DEHmldMRcQb8i+PiJsGcqi1FZwXCRq+IWRos29hetQ6rz5X3+FTDLorkMD2wg
         IhqgVBamvi/q6pOsOfBYx8wmeUaEK3gRtAE8s1udVTWXLIJsrRtKqGdkaa4805Bpp2wT
         mXD9fL6FdbrlGOuiuQVcTtDAbbOIMiQmrDMb8Rrb+OYUTVG8firBLnvvw4NklIryThoH
         Moyf5SXaDMmze/8c0hJz62KnCKySu87XhZhRkyz86Bp84RLDQAhsZZRktzMNomCQtxWm
         E4fOa6M+XwOAdopJHaFmVRwTMIJ9Q7OnXGD9+G+xU9aK5Ussu13+pnX/USA0dlQnFLtE
         K2jw==
ARC-Authentication-Results: i=1; mx.google.com;
       spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org;
       dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com
Return-Path: <linux-kernel-owner@vger.kernel.org>
Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67])
        by mx.google.com with ESMTP id x69-v6si2084816pfe.318.2018.08.02.06.44.40;
        Thu, 02 Aug 2018 06:44:54 -0700 (PDT)
Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
Authentication-Results: mx.google.com;
       spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org;
       dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
        id S1732278AbeHBOMY (ORCPT <rfc822;zoe.song.ucas@gmail.com>
        + 99 others); Thu, 2 Aug 2018 10:12:24 -0400
Received: from hqemgate14.nvidia.com ([216.228.121.143]:5873 "EHLO
        hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org
        with ESMTP id S1728797AbeHBOMX (ORCPT
        <rfc822;linux-kernel@vger.kernel.org>);
        Thu, 2 Aug 2018 10:12:23 -0400
Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1, AES128-SHA)
        id <B5b62f7390000>; Thu, 02 Aug 2018 05:21:15 -0700
Received: from HQMAIL101.nvidia.com ([172.20.161.6])
  by hqpgpgate101.nvidia.com (PGP Universal service);
  Thu, 02 Aug 2018 05:21:27 -0700
X-PGP-Universal: processed;
        by hqpgpgate101.nvidia.com on Thu, 02 Aug 2018 05:21:27 -0700
Received: from [10.21.132.122] (172.20.13.39) by HQMAIL101.nvidia.com
 (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 2 Aug
 2018 12:21:22 +0000
Subject: Re: [PATCH 1/3] soc/tegra: pmc: set IO pad power state and voltage
 via pinctrl fw
To:     Venkat Reddy Talla <vreddytalla@nvidia.com>, <airlied@linux.ie>,
        <dri-devel@lists.freedesktop.org>, <pdeschrijver@nvidia.com>,
        <vivek.gautam@codeaurora.org>, <p.zabel@pengutronix.de>,
        <thierry.reding@gmail.com>, <mperttunen@nvidia.com>,
        <mark.rutland@arm.com>, <robh+dt@kernel.org>,
        <devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>
CC:     <avienamo@nvidia.com>, <talho@nvidia.com>, <ldewangan@nvidia.com>
References: <1533211143-17517-1-git-send-email-vreddytalla@nvidia.com>
From:   Jon Hunter <jonathanh@nvidia.com>
Message-ID: <76f4442e-842b-c08f-386d-a7062ed34a19@nvidia.com>
Date:   Thu, 2 Aug 2018 13:21:20 +0100
User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101
 Thunderbird/52.9.1
MIME-Version: 1.0
In-Reply-To: <1533211143-17517-1-git-send-email-vreddytalla@nvidia.com>
X-Originating-IP: [172.20.13.39]
X-ClientProxiedBy: HQMAIL103.nvidia.com (172.20.187.11) To
 HQMAIL101.nvidia.com (172.20.187.10)
Content-Type: text/plain; charset="utf-8"
Content-Language: en-US
Content-Transfer-Encoding: 7bit
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org


On 02/08/18 12:59, Venkat Reddy Talla wrote:
> The IO pins of Tegra SoCs are grouped for common control
> of IO interface like setting voltage signal levels and
> power state of the interface. These groups are referred
> to as IO pads.The power state and voltage control of IO pins
> can be done at IO pads level.
> 
> Tegra SoCs support powering down IO pads when they are
> not used even in the active state of system.
> This saves power from that IO interface. Also it supports
> multiple voltage level in IO pins for interfacing on
> some of pads. The IO pad voltage is automatically detected
> till Tegra124, hence SW need not to configure this.
> But from Tegra210, the automatic detection logic has been
> removed, hence SW need to explicitly set the IO pad
> voltage into IO pad configuration registers.
> 
> Add support to configure the power state and voltage level
> of the IO pads from client driver via pincontrol framework.
> 
> Signed-off-by: Venkat Reddy Talla <vreddytalla@nvidia.com>

This appears to be a duplicate effort of the following which we have
been reviewing ...

https://marc.info/?l=linux-tegra&m=153295930808915&w=2

Cheers
Jon

-- 
nvpublic