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[209.132.180.67]) by mx.google.com with ESMTP id b5-v6si1730279pls.507.2018.08.02.11.06.29; Thu, 02 Aug 2018 11:06:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731606AbeHBSgJ (ORCPT + 99 others); Thu, 2 Aug 2018 14:36:09 -0400 Received: from mga05.intel.com ([192.55.52.43]:30410 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726938AbeHBSgI (ORCPT ); Thu, 2 Aug 2018 14:36:08 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 02 Aug 2018 09:44:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,436,1526367600"; d="scan'208";a="72050155" Received: from rchatre-mobl.amr.corp.intel.com (HELO [10.24.14.122]) ([10.24.14.122]) by orsmga003.jf.intel.com with ESMTP; 02 Aug 2018 09:44:13 -0700 Subject: Re: [PATCH 0/2] x86/intel_rdt and perf/x86: Fix lack of coordination with perf To: Peter Zijlstra Cc: tglx@linutronix.de, mingo@redhat.com, fenghua.yu@intel.com, tony.luck@intel.com, vikas.shivappa@linux.intel.com, gavin.hindman@intel.com, jithu.joseph@intel.com, dave.hansen@intel.com, hpa@zytor.com, x86@kernel.org, linux-kernel@vger.kernel.org References: <20180802123923.GJ2530@hirez.programming.kicks-ass.net> <1af731f8-b5d3-5aca-af02-575802a961b9@intel.com> <20180802161823.GJ2458@hirez.programming.kicks-ass.net> From: Reinette Chatre Message-ID: Date: Thu, 2 Aug 2018 09:44:13 -0700 User-Agent: Mozilla/5.0 (Windows NT 6.3; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.8.0 MIME-Version: 1.0 In-Reply-To: <20180802161823.GJ2458@hirez.programming.kicks-ass.net> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 8/2/2018 9:18 AM, Peter Zijlstra wrote: > On Thu, Aug 02, 2018 at 09:14:10AM -0700, Reinette Chatre wrote: > >> The current implementation does not coordinate with perf and this is >> what I am trying to fix in this series. >> >> I do respect your NAK but it is not clear to me how to proceed after >> obtaining it. Could you please elaborate on what you would prefer as a >> solution to ensure accurate measurement of cache-locked data that is >> better integrated? > > We have an in-kernel interface to perf, use that if you want access to > the PMU. You will not directly stomp on PMU registers. I do not see how I can do so without incurring the cache hits and misses from the data needed and instructions run by this interface. Could you please share how I can do so and still obtain the accurate measurement of cache residency of a specific memory region? Reinette