Received: by 2002:ac0:a5a7:0:0:0:0:0 with SMTP id m36-v6csp321959imm; Thu, 2 Aug 2018 20:05:45 -0700 (PDT) X-Google-Smtp-Source: AAOMgpeU5BDzng0jHlw1oSU90viGDbSrvXR3bNXGuJc7l2wBz3lZW5xrKgCjEhm4Idz8m3a64zQK X-Received: by 2002:a63:2dc1:: with SMTP id t184-v6mr1908448pgt.62.1533265545230; Thu, 02 Aug 2018 20:05:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533265545; cv=none; d=google.com; s=arc-20160816; b=oWaCWwXS/UfPuyXkQEH9aZqVNVuZJRzdvsbVG8QmFJLDaPDOUtEPPVxIZ/eRb/vIkQ SUhXyD9R+PVjOWiw3WH3IH/q61ItlvPgIzhGtVhPdGODjE3IZRVlJ4EOJrZ0CcTZpKG5 JVAc9qfKM5dXk42OKI3vkRBDhZc3QUCGk7mI/6Nrl3jeAvgeMD3Mqj9Hb3OaNZ/KVc5m 1GK4xZ5jiqbMGFtJWAcy8tHANlopqCXcjjdyivaheoR423j9nk2yIcyhNdY5ZODjyuAF rqWh2ddr5QMaqOOA+gY54JDmZh5gLx7BIAZIeF3nnuoCCw1LGFGPKyPcVdGCmo7u2qn8 ivhQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=i23yGj4J7V3ItqT5B0Z8+ln+LgLc5EllhenUzv2OtKM=; b=AoTURqhKnwtCJhpqARfwVMjf4oKw4FPHf/Cm6sXTaeNwWVV25HqesKjk8ffzscw2jt 4EXuPsi8VKcxgd5dZtS2FBn02CaowZzLJLzuRp/JfwcYQbGOsDNFl/Ne10SiJrJ0v8OA GrHPrmhFhLXJK0iu5cvhg42/ibLDITWshCgAPRc0GZwrG0XXXvzLuOUHX1v5VbIjlBfL Jb+/nY2zztqKG6UXC1T1cNMfDFH9IaYRvg0PuWoNvpHlyWcPiXIspPauA75k9237tHsP 2OS0L/NEVA6QVe6mcl9Vl5mbEoznQMZ/8zECdw26TPLFA76lqvVF+rd8BD9zZfAeFM21 1+8A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l9-v6si2979872pgp.503.2018.08.02.20.05.30; Thu, 02 Aug 2018 20:05:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727953AbeHCE56 (ORCPT + 99 others); Fri, 3 Aug 2018 00:57:58 -0400 Received: from mga17.intel.com ([192.55.52.151]:48918 "EHLO mga17.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727246AbeHCE56 (ORCPT ); Fri, 3 Aug 2018 00:57:58 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 02 Aug 2018 20:03:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,437,1526367600"; d="scan'208";a="78325507" Received: from sgsxdev001.isng.intel.com (HELO localhost) ([10.226.88.11]) by orsmga001.jf.intel.com with ESMTP; 02 Aug 2018 20:03:47 -0700 From: Songjun Wu To: hua.ma@linux.intel.com, yixin.zhu@linux.intel.com, chuanhua.lei@linux.intel.com, qi-ming.wu@intel.com Cc: linux-mips@linux-mips.org, linux-clk@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, Songjun Wu , James Hogan , linux-kernel@vger.kernel.org, Paul Burton , Rob Herring , Ralf Baechle , Mark Rutland Subject: [PATCH v2 05/18] dt-binding: MIPS: Add documentation of Intel MIPS SoCs Date: Fri, 3 Aug 2018 11:02:24 +0800 Message-Id: <20180803030237.3366-6-songjun.wu@linux.intel.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180803030237.3366-1-songjun.wu@linux.intel.com> References: <20180803030237.3366-1-songjun.wu@linux.intel.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Hua Ma This patch adds binding documentation for the compatible values of the Intel MIPS SoCs. Signed-off-by: Hua Ma Signed-off-by: Songjun Wu --- Changes in v2: - New patch split from previous patch - Add the board and chip compatible in dt document Documentation/devicetree/bindings/mips/intel.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/mips/intel.txt diff --git a/Documentation/devicetree/bindings/mips/intel.txt b/Documentation/devicetree/bindings/mips/intel.txt new file mode 100644 index 000000000000..ac594ef303b7 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/intel.txt @@ -0,0 +1,17 @@ +Intel MIPS SoC device tree bindings + +1, SoCs + +Each device tree must specify a compatible value for the Intel SoC +it uses in the compatible property of the root node. The compatible +value must be one of the following values: + + intel,xrx500 + +2, Boards + +Each device tree must specify a compatible value for the Intel Board +it uses in the compatible property of the root node. The compatible +value must be one of the following values: + + intel,easy350-anywan -- 2.11.0