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[209.132.180.67]) by mx.google.com with ESMTP id r24-v6si4927554pgo.295.2018.08.03.08.21.32; Fri, 03 Aug 2018 08:21:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727595AbeHCRRS (ORCPT + 99 others); Fri, 3 Aug 2018 13:17:18 -0400 Received: from mga03.intel.com ([134.134.136.65]:22003 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726485AbeHCRRS (ORCPT ); Fri, 3 Aug 2018 13:17:18 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 Aug 2018 08:20:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,439,1526367600"; d="scan'208";a="61855850" Received: from rchatre-mobl.amr.corp.intel.com (HELO [10.252.128.249]) ([10.252.128.249]) by orsmga007.jf.intel.com with ESMTP; 03 Aug 2018 08:18:10 -0700 Subject: Re: [PATCH 0/2] x86/intel_rdt and perf/x86: Fix lack of coordination with perf To: Peter Zijlstra Cc: Dave Hansen , tglx@linutronix.de, mingo@redhat.com, fenghua.yu@intel.com, tony.luck@intel.com, vikas.shivappa@linux.intel.com, gavin.hindman@intel.com, jithu.joseph@intel.com, hpa@zytor.com, x86@kernel.org, linux-kernel@vger.kernel.org References: <20180802123923.GJ2530@hirez.programming.kicks-ass.net> <1af731f8-b5d3-5aca-af02-575802a961b9@intel.com> <20180802161823.GJ2458@hirez.programming.kicks-ass.net> <20180802173727.GP2494@hirez.programming.kicks-ass.net> <653e874f-5e77-a9b5-996a-ed9daa3c6d43@intel.com> <20180802195410.GR2494@hirez.programming.kicks-ass.net> <20180802201312.GS2494@hirez.programming.kicks-ass.net> <086b93f5-da5b-b5e5-148a-cef25117b963@intel.com> <20180803104956.GU2494@hirez.programming.kicks-ass.net> From: Reinette Chatre Message-ID: <1eece033-fbae-c904-13ad-1904be91c049@intel.com> Date: Fri, 3 Aug 2018 08:18:09 -0700 User-Agent: Mozilla/5.0 (Windows NT 6.3; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.8.0 MIME-Version: 1.0 In-Reply-To: <20180803104956.GU2494@hirez.programming.kicks-ass.net> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Peter, On 8/3/2018 3:49 AM, Peter Zijlstra wrote: > On Thu, Aug 02, 2018 at 01:43:42PM -0700, Reinette Chatre wrote: > >> The goal of this work is to use the existing PMU hardware coordination >> mechanism to ensure that perf and resctrl will not interfere with each >> other. > > I understand what it does.. but if I'd seen you frobbing at the PMU > earlier your patches would've never gotten merged. > > It's simply not going to happen. Your two-fold guidance is clear to me: (1) do not use PMU registers directly, (2) use perf API instead. You state that you understand what we are trying to do and I hope that I convinced you that we are not able to accomplish the same by following your guidance. Could you please guide us how to obtain the accurate results we obtain at this time while satisfying your requirements? Earlier your response to a similar question was "That's the best you're going to get" - unfortunately I cannot respectfully say that to our customers when they indeed have become used to working with accurate data for more than a year. I really want to find a solution that is acceptable to mainline instead of having to maintain a solution needed by customers out of tree. Reinette