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[209.132.180.67]) by mx.google.com with ESMTP id a74-v6si5897974pfe.301.2018.08.03.10.25.56; Fri, 03 Aug 2018 10:26:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CIJJOUvd; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728687AbeHCTWW (ORCPT + 99 others); Fri, 3 Aug 2018 15:22:22 -0400 Received: from mail-it0-f65.google.com ([209.85.214.65]:54829 "EHLO mail-it0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728116AbeHCTWW (ORCPT ); Fri, 3 Aug 2018 15:22:22 -0400 Received: by mail-it0-f65.google.com with SMTP id s7-v6so9301042itb.4 for ; Fri, 03 Aug 2018 10:25:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=X2NAUnRoIsdwobCyBEqidc4JYudFIVHILUTepkSMRVs=; b=CIJJOUvdhUdBbggU3H/RbZDBcfx6mSVFczc15Kh+AvoUIQwII1kzAvXbH+bNfO4LbF aA2kKTiP8J/RlDMjAugzKVigJY4J1WW9KLHGHcbqVAfdglRcEARuKviKfPS7AwAXljZw ra5WccZ44D65IulWK3sTy6pm+WpEW8OV+deCw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=X2NAUnRoIsdwobCyBEqidc4JYudFIVHILUTepkSMRVs=; b=aq9PiyqFq2fUKiQCLA75yBaYV+NH5cNTA2P9bF2LY1gayiDminyV6DfQjlcqlLVph4 xjdslAw7oMVgbb4RcKE9rOGbVfeQzYLxe4MxcXr+QKwvUVjifnH9U5l5UovadjpwEx24 u+QfUwJ7D6cL3uDzMO2WJuCPRRpzcYqGSVEgaMDjo02wupwUgJyQ5OFyKhC3qElnqP9a vndHrgPN214igASdNysDka1EhXgj0Hnxvxb5EsP06ekCYf4SOVd0rXGcOXA9z7ScJ0xc rs3enq/AqT2wBQxD6q7QEpDDLC3E2848cUyj2Xg9kcVA7PwAoV2+j2yVw5+a/dWWaE/G MtQA== X-Gm-Message-State: AOUpUlGUQ0WnuKIs+Gh7cSvIL8/NmJZY14KObP18BvT6J91WmVW3r/FN +up7sy1LVTVFXBZUS5lY204U0N7aURppR72IR78b9A== X-Received: by 2002:a02:2505:: with SMTP id g5-v6mr4234089jag.112.1533317109011; Fri, 03 Aug 2018 10:25:09 -0700 (PDT) MIME-Version: 1.0 References: <20180802111144.12512-1-digetx@gmail.com> <20a52a0461e32e776e526171c250551a@agner.ch> In-Reply-To: <20a52a0461e32e776e526171c250551a@agner.ch> From: Linus Walleij Date: Fri, 3 Aug 2018 19:24:56 +0200 Message-ID: Subject: Re: [PATCH v1 1/2] pinctrl: tegra: Move drivers registration to arch_init level To: Stefan Agner Cc: Dmitry Osipenko , "thierry.reding@gmail.com" , Jon Hunter , Marcel Ziswiler , linux-tegra@vger.kernel.org, "open list:GPIO SUBSYSTEM" , "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Aug 2, 2018 at 1:31 PM Stefan Agner wrote: > A while back at least using those init lists were not well received even > for GPIO/pinctrl drivers: > > https://lore.kernel.org/lkml/CACRpkdYk0zW12qNXgOstTLmdVDYacu0Un+8quTN+J_azOic7AA@mail.gmail.com/T/#mf0596982324a6489b5537b0531ac5aed60a316ba You shouldn't listen too much to that guy he's not trustworthy. > I still think we should make an exception for GPIO/pinctrl and use > earlier initcalls. Platform GPIO/pinctrl drivers provide basic > infrastructure often used by many other drivers, we want to have them > loaded early. It avoids unnecessary EPROBE_DEFER and hence probably even > boots faster. When we have the pin control and GPIO at different initlevels it makes me uneasy because I feel we have implicit init dependencies that seem more than a little fragile. My recent thinking has involved the component method used in DRM drivers such as drivers/gpu/drm/vc4/vc4_drv.c where a few different component subdrivers are linked together at bind time (not probe time!) into a master component. Rob was no big fan of this but the DRM people like it and I was thinking to make a try at it. This way we could at least probe and bind the pin control and GPIO drivers at the *same* initlevel and express the dependencies between them somewhat. > This should definitely go in, at least as a stop gap solution. Agreed. (And patch applied.) Yours, Linus Walleij