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[209.132.180.67]) by mx.google.com with ESMTP id e132-v6si13274082pfg.171.2018.08.06.02.00.20; Mon, 06 Aug 2018 02:00:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727743AbeHFLG6 (ORCPT + 99 others); Mon, 6 Aug 2018 07:06:58 -0400 Received: from mga01.intel.com ([192.55.52.88]:39415 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726537AbeHFLG5 (ORCPT ); Mon, 6 Aug 2018 07:06:57 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Aug 2018 01:58:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,451,1526367600"; d="scan'208";a="70501551" Received: from songjunw-mobl1.ger.corp.intel.com (HELO [10.226.39.42]) ([10.226.39.42]) by FMSMGA003.fm.intel.com with ESMTP; 06 Aug 2018 01:58:50 -0700 Subject: Re: [PATCH v2 14/18] serial: intel: Add CCF support To: Geert Uytterhoeven Cc: Arnd Bergmann , Greg KH , Hauke Mehrtens , hua.ma@linux.intel.com, yixin.zhu@linux.intel.com, chuanhua.lei@linux.intel.com, qi-ming.wu@intel.com, Linux MIPS Mailing List , linux-clk , "open list:SERIAL DRIVERS" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Linux Kernel Mailing List , Jiri Slaby References: <20180803030237.3366-1-songjun.wu@linux.intel.com> <20180803030237.3366-15-songjun.wu@linux.intel.com> <20180803055640.GA32226@kroah.com> <763bba56-3701-7fe9-9b31-4710594b40d5@linux.intel.com> <20180803103023.GA6557@kroah.com> <3360edd2-f3d8-b860-13fa-ce680edbfd0a@hauke-m.de> <20180804124309.GB4920@kroah.com> From: "Wu, Songjun" Message-ID: <0ab8e6e7-3cc2-8e50-b1f3-99616437f527@linux.intel.com> Date: Mon, 6 Aug 2018 16:58:49 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 8/6/2018 3:20 PM, Geert Uytterhoeven wrote: > Hi Songjun, > > On Mon, Aug 6, 2018 at 9:15 AM Wu, Songjun wrote: >> On 8/5/2018 5:03 AM, Arnd Bergmann wrote: >>> On Sat, Aug 4, 2018 at 2:43 PM, Greg Kroah-Hartman >>> wrote: >>>> On Sat, Aug 04, 2018 at 12:54:22PM +0200, Hauke Mehrtens wrote: >>>>> On 08/03/2018 12:30 PM, Greg Kroah-Hartman wrote: >>>>>> On Fri, Aug 03, 2018 at 03:33:38PM +0800, Wu, Songjun wrote: >>>>> This patch makes it possible to use it with the legacy lantiq code and >>>>> also with the common clock framework. I see multiple options to fix this >>>>> problem. >>>>> >>>>> 1. The current approach to have it as a compile variant for a) legacy >>>>> lantiq arch code without common clock framework and b) support for SoCs >>>>> using the common clock framework. >>>>> 2. Convert the lantiq arch code to the common clock framework. This >>>>> would be a good approach, but it need some efforts. >>>>> 3. Remove the arch/mips/lantiq code. There are still users of this code. >>>>> 4. Use the old APIs also for the new xRX500 SoC, I do not like this >>>>> approach. >>>>> 5. Move lantiq_soc.h to somewhere in include/linux/ so it is globally >>>>> available and provide some better wrapper code. >>>> I don't really care what you do at this point in time, but you all >>>> should know better than the crazy #ifdef is not allowed to try to >>>> prevent/allow the inclusion of a .h file. Checkpatch might have even >>>> warned you about it, right? >>>> >>>> So do it correctly, odds are #5 is correct, as that makes it work like >>>> any other device in the kernel. You are not unique here. >>> The best approach here would clearly be 2. We don't want platform >>> specific header files for doing things that should be completely generic. >>> >>> Converting lantiq to the common-clk framework obviously requires >>> some work, but then again the whole arch/mips/lantiq/clk.c file >>> is fairly short and maybe not that hard to convert. >>> >>> >From looking at arch/mips/lantiq/xway/sysctrl.c, it appears that you >>> already use the clkdev lookup mechanism for some devices without >>> using COMMON_CLK, so I would assume that you can also use those >>> for the remaining clks, which would be much simpler. It registers >>> one anonymous clk there as >>> >>> clkdev_add_pmu("1e100c00.serial", NULL, 0, 0, PMU_ASC1); >>> >>> so why not add replace that with two named clocks and just use >>> the same names in the DT for the newer chip? >>> >>> Arnd >> We discussed internally and have another solution for this issue. >> Add one lantiq.h in the serial folder, and use "#ifdef preprocessor" in >> lantiq.h, >> also providing no-op stub functions in the #else case, then call those >> functions >> unconditionally from lantiq.c to avoid #ifdef in C file. >> >> To support CCF in legacy product is another topic, is not included in >> this patch. >> >> The implementation is as following: >> #ifdef CONFIG_LANTIQ >> #include >> #else >> #define LTQ_EARLY_ASC 0 >> #define CPHYSADDR(_val) 0 >> >> static inline struct clk *clk_get_fpi(void) >> { >> return NULL; >> } >> #endif > Why not use clkdev_add(), as Arnd suggested? > That would be a 3-line patch without introducing a new header file and an ugly > #ifdef, which complicates compile coverage testing? > > Gr{oetje,eeting}s, > > Geert The reason we add a new head file is also for two macros(LTQ_EARLY_ASC and CPHYSADDR) used by legacy product. We need to provide the no-op stub for these two macro for new product.