Received: by 2002:ac0:a5a7:0:0:0:0:0 with SMTP id m36-v6csp917661imm; Wed, 8 Aug 2018 07:52:39 -0700 (PDT) X-Google-Smtp-Source: AA+uWPynpsbexHYF76wWg+M78/KhK8j/298Lgn/Cg5qB6FkUyby3d+v5OmqcOP5fZz494b+AaViN X-Received: by 2002:a17:902:4081:: with SMTP id c1-v6mr2897612pld.169.1533739959612; Wed, 08 Aug 2018 07:52:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533739959; cv=none; d=google.com; s=arc-20160816; b=EzdvnShFIfMDzoVVyHQSPD8zNWiAOsqMKQhkjr+sW0lxgZPoONVshPLX1Ts3LHKyWH qL5pL0C1aB6kot4dYduLGEOsxgGZ9AxVVx0K0bnUKWAVXcf6Ief4Bzipf4m6f9i/+aqt nh1BYThE7zbotLao48x4tAwlYNnE8P9Dpm8bUHak7woXuzTeF9IfwMn+cC+CCYK4oAiv ov4dy43c7ajZ46/qy/n7SPOE1N03TYV+wNylv3usXdXJJItGaDJLh2JUBHFRkfXFyrgL jsm+ru1x5L/155PekuiiIY2onT5RGdOs6sD7rAa8jxS7ixb6FjHOIpQRHyp0EAmYvcud RsuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:user-agent:in-reply-to :content-disposition:mime-version:references:mail-followup-to :message-id:subject:cc:to:from:date:dmarc-filter:dkim-signature :dkim-signature:arc-authentication-results; bh=lwQT9922kgTTrldxdepR3rtjJcjKf7mLOPs9PHs5pIU=; b=GPVeGCjkQxGctQHsX+ovELP5+/cn5lNucFkGQvdYsyfDdQkgmKSlbiBZrKDh8pzNph KcYgORA3lgydO7z5vgfCZeSftIAWNeVt0UKzabQ4ZZnWrw4WHJmkz2NZ/bCCcVWeIutk cfzZn4QWcSpBHlYkMnioWzmoWozdCZpKSdWLp2rqfaaX6Qpe4ygmLoHAH2CTJ1X3xOXn wl5jylTdHBOnPnSbmDy+lwp7xH0HCRrD7wgcfw9eZaXhxu1gclMMLSvbHcI+0hDMkFGg +wQavd2gQrLLLyBYKnfWzoTUYqfkT3/1wOXlQ2f3A+hXpqP8pCnCDDyRHYZ6DVJ3p7x1 QqPg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=TDuAuWbc; dkim=pass header.i=@codeaurora.org header.s=default header.b=TDuAuWbc; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z15-v6si4528920pga.117.2018.08.08.07.52.25; Wed, 08 Aug 2018 07:52:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=TDuAuWbc; dkim=pass header.i=@codeaurora.org header.s=default header.b=TDuAuWbc; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727535AbeHHRL3 (ORCPT + 99 others); Wed, 8 Aug 2018 13:11:29 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:36072 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727141AbeHHRL2 (ORCPT ); Wed, 8 Aug 2018 13:11:28 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id E8CCB60B22; Wed, 8 Aug 2018 14:51:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1533739886; bh=hkmAnBrpNhVQ5foFo6dw2cItSSVoZMcYa8dfWLVEhl8=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=TDuAuWbcSIUOPbIaF7f+rm/ra+1lExl+O6XH6Qe/53IRI2iAKJlGXBRmbPuOiCy4+ 31cGcZ6urefjd4ee+FkGS3SOTEEQYv3t3O+mU4+KLyAKdm0qKWjcYcCplKeqBJ7CD+ OSe/ZKsiDebSvC1sEh4PY3DnjajtaH8KV2kYjWpk= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from jcrouse-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 869D5607C6; Wed, 8 Aug 2018 14:51:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1533739886; bh=hkmAnBrpNhVQ5foFo6dw2cItSSVoZMcYa8dfWLVEhl8=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=TDuAuWbcSIUOPbIaF7f+rm/ra+1lExl+O6XH6Qe/53IRI2iAKJlGXBRmbPuOiCy4+ 31cGcZ6urefjd4ee+FkGS3SOTEEQYv3t3O+mU4+KLyAKdm0qKWjcYcCplKeqBJ7CD+ OSe/ZKsiDebSvC1sEh4PY3DnjajtaH8KV2kYjWpk= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 869D5607C6 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org Date: Wed, 8 Aug 2018 08:51:23 -0600 From: Jordan Crouse To: Stephen Boyd Cc: Amit Nischal , Michael Turquette , Andy Gross , David Brown , Rajendra Nayak , Odelu Kukatla , Taniya Das , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk-owner@vger.kernel.org Subject: Re: [PATCH 2/4] clk: qcom: Add clk_rcg2_gfx3d_ops for SDM845 Message-ID: <20180808145123.GA18086@jcrouse-lnx.qualcomm.com> Mail-Followup-To: Stephen Boyd , Amit Nischal , Michael Turquette , Andy Gross , David Brown , Rajendra Nayak , Odelu Kukatla , Taniya Das , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk-owner@vger.kernel.org References: <1528285308-25477-1-git-send-email-anischal@codeaurora.org> <1528285308-25477-3-git-send-email-anischal@codeaurora.org> <153111693472.143105.11303543263643845656@swboyd.mtv.corp.google.com> <1e6d9fc284c3c118203728867f504ec6@codeaurora.org> <153250192252.48062.9210075387954345932@swboyd.mtv.corp.google.com> <07e0321116993d27d6585bd1a186328d@codeaurora.org> <153324986956.10763.5124619734269160725@swboyd.mtv.corp.google.com> <20180806150437.GE21283@jcrouse-lnx.qualcomm.com> <153370789988.220756.1656616273823792690@swboyd.mtv.corp.google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <153370789988.220756.1656616273823792690@swboyd.mtv.corp.google.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Aug 07, 2018 at 10:58:19PM -0700, Stephen Boyd wrote: > Quoting Jordan Crouse (2018-08-06 08:04:37) > > On Mon, Aug 06, 2018 at 02:37:18PM +0530, Amit Nischal wrote: > > > On 2018-08-03 04:14, Stephen Boyd wrote: > > > >Quoting Amit Nischal (2018-07-30 04:28:56) > > > >>On 2018-07-25 12:28, Stephen Boyd wrote: > > > >>> > > > >>> Ok. Sounds good! Is the rate range call really needed? It can't be > > > >>> determined in the PLL code with some table or avoided by making sure > > > >>> GPU > > > >>> uses OPP table with only approved frequencies? > > > >>> > > > >> > > > >>Currently fabia PLL code does not have any table to check this and > > > >>intention > > > >>was to avoid relying on the client to call set_rate with only approved > > > >>frequencies so we have added the set_rate_range() call in the GPUCC > > > >>driver > > > >>in order to set the rate range. > > > >> > > > > > > > >But GPU will use OPP so it doesn't seem like it really buys us anything > > > >here. And it really doesn't matter when the clk driver implementation > > > >doesn't use the min/max to clamp the values of the round_rate() > > > >call. Is > > > >that being done here? I need to double check. I would be more convinced > > > >if the implementation was looking at min/max to constrain the rate > > > >requested. > > > > > > > > > > So our understanding is that GPU(client) driver will always call the > > > set_rate with approved frequencies only and we can completely rely > > > on the > > > client. Is our understanding is correct? > > > > > > First: on sdm845 the software doesn't set the GPU clocks - we rely on the GMU > > firmware to do that on our behalf but for the GPU at least this is an academic > > exercise. > > So what is this GPU clk driver for then? That is a good question. There is a hodgepodge of clocks for the GMU, GPU and SMMU and I'm not sure which ones are provided by the various clk drivers. This isn't my area of expertise. The GMU uses: GPU_CC_CX_GMU_CLK GPU_CC_CXO_CLK GCC_DDRSS_GPU_AXI_CLK GCC_GPU_MEMNOC_GFX_CLK These are controlled by the GMU device. The SMMU uses: GCC_GPU_CFG_AHB_CLK GCC_DDRSS_GPU_AXI_CLK GCC_GPU_MEMNOC_GFX_CLK These should be controlled by the SMMU device. Downstream defines these drivers for the GPU but we don't get/prepare/use them for the GPU device - I think they are there in case the GMU isn't working or is disabled for some other reason. GPU_CC_GX_GFX3D_CLK GPU_CC_CXO_CLK GCC_DDRSS_GPU_AXI_CLK GCC_GPU_MEMNOC_GFX_CLK GPU_CC_CX_GMU_CLK > > > > But that said: traditionally we've expected that the clock driver correctly > > clamp the requested rate to the correct values. In the past we have taken > > advantage of this and we may in the future. I don't think it is reasonable > > to require the leaf driver to only pass "approved" frequencies especially > > since we depend on our own OPP table that may or may not be similar to the > > one used by the clock driver. > > > > Ok. Sounds like things can't be kept in sync between the clk driver and > the OPP tables. Why is that hard to do? Again, not my area of expertise. Traditionally the leaf driver is responsible for setting its own OPP table. I'm not sure if the clock driver can or should be in the role of switching up the table. We've always assumed that the clk driver will sanity check whatever we ask it for. Jordan -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project