Received: by 2002:ac0:a5a7:0:0:0:0:0 with SMTP id m36-v6csp920514imm; Wed, 8 Aug 2018 07:55:29 -0700 (PDT) X-Google-Smtp-Source: AA+uWPyJPY+om/z+i1ryP2gsXmWipgARV0zqjcSYm702EkHdDzk736UMRy+OH0p83CQqdRNjTQQV X-Received: by 2002:a63:4b5a:: with SMTP id k26-v6mr2827792pgl.384.1533740129484; Wed, 08 Aug 2018 07:55:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533740129; cv=none; d=google.com; s=arc-20160816; b=Lx7wPaRzBEeu12g+06IBGgJHGKqHmoi9CGEi8sUHkTPHl9r1/mVNjyybGloUk5JxCX h6tupB8ZszouP8v/3HRJ6wPRpY0N3Vy2VP97cQVIJGzkskp3Z3+9buAYzWIwpnNwrYk4 Q8vp+Kc012InwRPrWFbSd5pAWPkahrj+zAkEpTzzaFHoO5eb9fazlhL0CstSsVFVDcYz ealEJee0b9CVjTV1gpGVy6QIUZodFvDv6BVlK5ivxkSvB2+vvbL6wy3YM3lRGPPZCQBQ fLXhOhE3omiX9EgVgB4VwI0zQgdKlJjmRfX33ePP8SaRzF+CWPUmrq8O76YMta3rlRXF G8lg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:dkim-signature :arc-authentication-results; bh=F5mbeqtJn4XZ3/40rWysQBTVz8+2bpgwzOdc0tVBPy4=; b=Cft/cM8ATUGKxM4dpXz/l0MBbNto44NIFePeIHqU3bDKAUoUFeN9Vu5EO8ukaOv72y tMuI0x/1Kdw0BA1MP06mt96eCNDiaCBGDx+ChCbXyPbOiyS2NQLIv99u1VlMl5/G/Gvb Dby5gcvH7YKJHBLOrHrTzeK2+W0twl/38Jb7YQQHam39PqiexeBVCpHKLnDns5c0+0hJ 5yZW41GZ09gf5hf3QV5/ePURQ7mD0SAHiM8x3K2dOhuX8UlZnCEQB5+e4RJ9G4bUM8aT kLoxalIq/238ogf/9TRtPDw497RafAlHvu3DeKD0o2Vq/PDNqVhZiByaV5P1MeOBKaL9 EG4A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=NMTgIVCU; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i13-v6si4338499pgh.642.2018.08.08.07.55.14; Wed, 08 Aug 2018 07:55:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=NMTgIVCU; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727531AbeHHRO0 (ORCPT + 99 others); Wed, 8 Aug 2018 13:14:26 -0400 Received: from mail.kernel.org ([198.145.29.99]:47044 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727108AbeHHRO0 (ORCPT ); Wed, 8 Aug 2018 13:14:26 -0400 Received: from mail-qt0-f175.google.com (mail-qt0-f175.google.com [209.85.216.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 9049621A11; Wed, 8 Aug 2018 14:54:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1533740064; bh=Pahyq1tM2+wFi1p1aQch8rJ41izJQ8sVjNLwI7RmDUs=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=NMTgIVCUBa+7M82LNHE+1IQyo5Ow9Hi/DcPoY8zD3dED/ONewNCjpV1kst1r7K0gJ 7CTPaAc3xI/jbBZgFh0mkBaY9gZ65bECp9YHRXIrJ3gnVO/DiBtaaNeA2CFS2YW8o0 OiegRBm6D3apMheW5mKL54oSOZtopJs22u/mHqNM= Received: by mail-qt0-f175.google.com with SMTP id y5-v6so2678698qti.12; Wed, 08 Aug 2018 07:54:24 -0700 (PDT) X-Gm-Message-State: AOUpUlFdiD/hNC/alSE3LrerKrREhEWMll7WDc8W0lNWRwXAkUNzUy3H im3z/szw+dMqbcwdBCZ1mc6KSgnqwIHIEyc20A== X-Received: by 2002:ac8:71c9:: with SMTP id i9-v6mr2937972qtp.22.1533740063752; Wed, 08 Aug 2018 07:54:23 -0700 (PDT) MIME-Version: 1.0 References: <20180803030237.3366-1-songjun.wu@linux.intel.com> <20180803030237.3366-4-songjun.wu@linux.intel.com> <9c0cbdfa-8109-be0d-8e14-7d303c764f5c@linux.intel.com> In-Reply-To: <9c0cbdfa-8109-be0d-8e14-7d303c764f5c@linux.intel.com> From: Rob Herring Date: Wed, 8 Aug 2018 08:54:12 -0600 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 03/18] dt-bindings: clk: Add documentation of grx500 clock controller To: yixin zhu Cc: Songjun Wu , hua.ma@linux.intel.com, chuanhua.lei@linux.intel.com, qi-ming.wu@intel.com, Linux-MIPS , linux-clk , "open list:SERIAL DRIVERS" , devicetree@vger.kernel.org, Michael Turquette , Stephen Boyd , "linux-kernel@vger.kernel.org" , Mark Rutland Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Aug 7, 2018 at 9:08 PM yixin zhu wrote: > > > > On 8/6/2018 11:18 PM, Rob Herring wrote: > > On Thu, Aug 2, 2018 at 9:03 PM Songjun Wu wrote: > >> From: Yixin Zhu > >> > >> This patch adds binding documentation for grx500 clock controller. > >> > >> Signed-off-by: YiXin Zhu > >> Signed-off-by: Songjun Wu > >> --- > >> > >> Changes in v2: > >> - Rewrite clock driver's dt-binding document according to Rob Herring's > >> comments. > >> - Simplify device tree docoment, remove some clock description. > >> > >> .../devicetree/bindings/clock/intel,grx500-clk.txt | 39 ++++++++++++++++++++++ > > Please match the compatible string: intel,grx500-cgu.txt > Will update to use same name. > > > > >> 1 file changed, 39 insertions(+) > >> create mode 100644 Documentation/devicetree/bindings/clock/intel,grx500-clk.txt > >> > >> diff --git a/Documentation/devicetree/bindings/clock/intel,grx500-clk.txt b/Documentation/devicetree/bindings/clock/intel,grx500-clk.txt > >> new file mode 100644 > >> index 000000000000..e54e1dad9196 > >> --- /dev/null > >> +++ b/Documentation/devicetree/bindings/clock/intel,grx500-clk.txt > >> @@ -0,0 +1,39 @@ > >> +Device Tree Clock bindings for grx500 PLL controller. > >> + > >> +This binding uses the common clock binding: > >> + Documentation/devicetree/bindings/clock/clock-bindings.txt > >> + > >> +The grx500 clock controller supplies clock to various controllers within the > >> +SoC. > >> + > >> +Required properties for clock node > >> +- compatible: Should be "intel,grx500-cgu". > >> +- reg: physical base address of the controller and length of memory range. > >> +- #clock-cells: should be 1. > >> + > >> +Optional Propteries: > >> +- intel,osc-frequency: frequency of the osc clock. > >> +if missing, driver will use clock rate defined in the driver. > > This should use a fixed-clock node instead. > Yes, This is a fixed clock node registered in driver code. > The frequency of the fixed clock is designed to be overwritten by device > tree in case some one verify > clock driver in the emulation platform or in some cases frequency other > than driver defined one is preferred. Emulation platforms often need several hacks that shouldn't be upstream... > These kinds of cases are very rare. But I feel it would be better to > have a way to use customized frequency. > The frequency defined in device tree will overwritten driver defined > frequency before registering fixed-clock node. I don't think you understand what I meant. Add a DT node with "fixed-clock" compatible and have this node refer to it with "clocks" property. The frequency is still in DT, but uses the clock binding. Rob