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From:   "Luck, Tony" <tony.luck@intel.com>
To:     Peter Zijlstra <peterz@infradead.org>,
        "Chatre, Reinette" <reinette.chatre@intel.com>
CC:     "Hansen, Dave" <dave.hansen@intel.com>,
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        "Joseph, Jithu" <jithu.joseph@intel.com>,
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Subject: RE: [PATCH 0/2] x86/intel_rdt and perf/x86: Fix lack of
 coordination with perf
Thread-Topic: [PATCH 0/2] x86/intel_rdt and perf/x86: Fix lack of
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Date:   Wed, 8 Aug 2018 15:55:54 +0000
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> So _why_ doesn't this work? As said by Tony, that first call should
> prime the caches, so the second and third calls should not generate any
> misses.

How much code/data is involved? If there is a lot, then you may be unlucky
with cache coloring and the later parts of the "prime the caches" code path
may evict some lines loaded in the early parts.

-Tony