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[209.132.180.67]) by mx.google.com with ESMTP id i124-v6si5108560pfc.110.2018.08.08.09.49.41; Wed, 08 Aug 2018 09:49:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729614AbeHHTIQ (ORCPT + 99 others); Wed, 8 Aug 2018 15:08:16 -0400 Received: from foss.arm.com ([217.140.101.70]:42828 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727165AbeHHTIP (ORCPT ); Wed, 8 Aug 2018 15:08:15 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D389218A; Wed, 8 Aug 2018 09:47:44 -0700 (PDT) Received: from [10.4.13.119] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 30FCA3F5D4; Wed, 8 Aug 2018 09:47:42 -0700 (PDT) Subject: Re: [PATCH 03/11] dt-bindings: interrupt-controller: RISC-V PLIC documentation To: Christoph Hellwig , Rob Herring Cc: Palmer Dabbelt , atish.patra@wdc.com, Thomas Gleixner , Jason Cooper , Mark Rutland , devicetree@vger.kernel.org, Albert Ou , Anup Patel , "linux-kernel@vger.kernel.org" , linux-riscv@lists.infradead.org, Stafford Horne References: <20180808150938.GA32274@lst.de> From: Marc Zyngier Organization: ARM Ltd Message-ID: Date: Wed, 8 Aug 2018 17:47:40 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <20180808150938.GA32274@lst.de> Content-Type: text/plain; charset=utf-8 Content-Language: en-GB Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 08/08/18 16:09, Christoph Hellwig wrote: > On Wed, Aug 08, 2018 at 08:16:14AM -0600, Rob Herring wrote: >> Is 1.0 an actual version number corresponding to an exact, revision >> controlled version of the IP or just something you made up? Looks like >> the latter to me and I'm not a fan of s/w folks making up version >> numbers for h/w. Standard naming convention is ,- >> unless you have good reason to deviate (IP for FPGAs where version >> numbers are exposed to customers is one example). >> >> And defining a version 2 when you find a quirk doesn't work. You've >> already shipped the DT. You need to be able to fix issues with just an >> OS update. This is why you are supposed to define a compatible string >> for each and every SoC (and use a fallback when they are "the >> same"TM). > > Can you point to some existing examples of the multiple offered > compatible strings and what is actually matched for something that > largely hasn't changed? > > For example the documentation for the arm GICv3 binding seems to just > match for arm,gic-v3. On the other hand the GIC driver seems to match > for a lot of different strings. The original GIC driver deals with 2.5 revisions of the architecture (yes, there was something pre-GICv1...), and implementers have been creative to the extreme. Still, we could have done without most of these compat strings. Hindsight and all that jazz. GICv3 is a much more controlled architecture, and although people have come up with a number of turds masquerading as implementations, it has never been bad enough to mandate a different set of compat strings. Also, you cannot describe that kind of stuff in ACPI, and we need to support both, so we've come up with different ways of handling this. M. -- Jazz is not dead. It just smells funny...