Received: by 2002:ac0:a5a7:0:0:0:0:0 with SMTP id m36-v6csp1505835imm; Wed, 8 Aug 2018 19:17:45 -0700 (PDT) X-Google-Smtp-Source: AA+uWPz5CyuKf+a2xmlMz6DbFhNd61HxSUh6me+pFkbDjoKgN54UTk5nKb1aIoE8qfdYYp5vquKR X-Received: by 2002:a17:902:585:: with SMTP id f5-v6mr212293plf.7.1533781065448; Wed, 08 Aug 2018 19:17:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533781065; cv=none; d=google.com; s=arc-20160816; b=c34dZ6Q6cxgInSa6VQHtXN2Z+wRpmwJHgw2KqtjlR8lf4JHRG8winNCCTtYxBH6Y01 uPnVZ684OVaElKs8fxlhk5nRgK5kaI44rJmHiZd4dRtWavmHAAt7vrz3n2tHHgJD6Ijv 6cSlb6NaXqKcXXm2WoSRCEOgI8uI3w0H8uYvlEO16DgWSnPfFeaMMag05qqALaMw2DeG eubOSDGlIhL34JjmfRRqK0J+K9cfjDSVLO4ch7gNgxoL95JSl2Q9Ach4Zy61I5qmq6uT lTuyVIr/GPcHe5HxGxja8VVgFegEgWeImN19nm5kEP9doHoOJAM24P9XKksG0GPqe4/q PqSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=uZ8pgWCyjocrcnySb3X7JmUh7WPovsBsLfOUEG1VTcY=; b=0MHloRpvHQOhRXF0J3evsqCy8wP3opMHj/JbnZTE75rtwsvTRYHfmaFfKQ/bLBo997 P+GcgSJr4KkCdUkwq6nG6dXK3bQrA1LdaZNSTmehn6iT1q/5VLg+Bps+lUFho1hBWxnO 8zLxFSJpCtXV3mIBZEPhyBHw/lrWLGOEJRRC7mOD/Pqdu7cUjiPvPPqx5B7qONojLaDP bK3CeCfk+eXbVVCcqwd19Lwlu3FNn45xIfUIMZvOtD1OJJbgLTCg7CoNXr68nAZG8YU2 xRM0UO8/TPZt3usoj3qqxEoRmOdYZeurGLrroC/m1CFyTsQRb+2DMzPTFs1fsbb+yLMp hxSQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z3-v6si6056222pgl.579.2018.08.08.19.17.31; Wed, 08 Aug 2018 19:17:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728405AbeHIEig (ORCPT + 99 others); Thu, 9 Aug 2018 00:38:36 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:49144 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725779AbeHIEif (ORCPT ); Thu, 9 Aug 2018 00:38:35 -0400 X-UUID: 78fbb1f0aeba453388bef7ac4d3952ae-20180809 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1020796618; Thu, 09 Aug 2018 10:15:52 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Thu, 9 Aug 2018 10:15:51 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Thu, 9 Aug 2018 10:15:51 +0800 From: Stu Hsieh To: CK Hu , Philipp Zabel CC: David Airlie , Matthias Brugger , , , , , , Stu Hsieh Subject: [PATCH v4 06/14] drm/mediatek: add RGB color format support for RDMA Date: Thu, 9 Aug 2018 10:15:41 +0800 Message-ID: <1533780949-30141-7-git-send-email-stu.hsieh@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1533780949-30141-1-git-send-email-stu.hsieh@mediatek.com> References: <1533780949-30141-1-git-send-email-stu.hsieh@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch add RGB color format support for RDMA, including RGB565, RGB888, RGBA8888 and ARGB8888. Signed-off-by: Stu Hsieh --- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 46 ++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index 08866550740f..1f57f86c7910 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -35,6 +35,8 @@ #define DISP_REG_RDMA_SIZE_CON_0 0x0014 #define DISP_REG_RDMA_SIZE_CON_1 0x0018 #define DISP_REG_RDMA_TARGET_LINE 0x001c +#define DISP_RDMA_MEM_CON 0x0024 +#define MEM_MODE_INPUT_SWAP BIT(8) #define DISP_RDMA_MEM_SRC_PITCH 0x002c #define DISP_RDMA_MEM_GMC_SETTING_0 0x0030 #define DISP_REG_RDMA_FIFO_CON 0x0040 @@ -46,6 +48,11 @@ #define RDMA_MEM_GMC 0x40402020 +#define MEM_MODE_INPUT_FORMAT_RGB565 0x0 +#define MEM_MODE_INPUT_FORMAT_RGB888 (0x001 << 4) +#define MEM_MODE_INPUT_FORMAT_RGBA8888 (0x002 << 4) +#define MEM_MODE_INPUT_FORMAT_ARGB8888 (0x003 << 4) + struct mtk_disp_rdma_data { unsigned int fifo_size; }; @@ -144,12 +151,51 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON); } +static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma, + unsigned int fmt) +{ + /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX" + * is defined in mediatek HW data sheet. + * The alphabet order in XXX is no relation to data + * arrangement in memory. + */ + switch (fmt) { + default: + case DRM_FORMAT_RGB565: + return MEM_MODE_INPUT_FORMAT_RGB565; + case DRM_FORMAT_BGR565: + return MEM_MODE_INPUT_FORMAT_RGB565 | MEM_MODE_INPUT_SWAP; + case DRM_FORMAT_RGB888: + return MEM_MODE_INPUT_FORMAT_RGB888; + case DRM_FORMAT_BGR888: + return MEM_MODE_INPUT_FORMAT_RGB888 | MEM_MODE_INPUT_SWAP; + case DRM_FORMAT_RGBX8888: + case DRM_FORMAT_RGBA8888: + return MEM_MODE_INPUT_FORMAT_ARGB8888; + case DRM_FORMAT_BGRX8888: + case DRM_FORMAT_BGRA8888: + return MEM_MODE_INPUT_FORMAT_ARGB8888 | MEM_MODE_INPUT_SWAP; + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_ARGB8888: + return MEM_MODE_INPUT_FORMAT_RGBA8888; + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_ABGR8888: + return MEM_MODE_INPUT_FORMAT_RGBA8888 | MEM_MODE_INPUT_SWAP; + } +} + static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, struct mtk_plane_state *state) { + struct mtk_disp_rdma *rdma = comp_to_rdma(comp); struct mtk_plane_pending_state *pending = &state->pending; unsigned int addr = pending->addr; unsigned int pitch = pending->pitch & 0xffff; + unsigned int fmt = pending->format; + unsigned int con; + + con = rdma_fmt_convert(rdma, fmt); + writel_relaxed(con, comp->regs + DISP_RDMA_MEM_CON); writel_relaxed(addr, comp->regs + DISP_RDMA_MEM_START_ADDR); writel_relaxed(pitch, comp->regs + DISP_RDMA_MEM_SRC_PITCH); -- 2.12.5.2.gbdf23ab