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[209.132.180.67]) by mx.google.com with ESMTP id i123-v6si6724070pfe.145.2018.08.09.01.51.28; Thu, 09 Aug 2018 01:51:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b="S+j/vm9t"; dkim=pass header.i=@codeaurora.org header.s=default header.b=C4Ohh0Au; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729837AbeHILOX (ORCPT + 99 others); Thu, 9 Aug 2018 07:14:23 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:37900 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727579AbeHILOX (ORCPT ); Thu, 9 Aug 2018 07:14:23 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 99B6760B77; Thu, 9 Aug 2018 08:50:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1533804632; bh=bmTsXFgWnM32PaUKbXlD+i/H5+ixoWxvafxcJ7mubus=; h=Subject:To:Cc:References:From:Date:In-Reply-To:From; b=S+j/vm9tyP6D5BhYIVH2UjWM4kFHSGSze9GPmlkzJdCWyd/ZmiS04s4hdcmcRtzWN Kohqi2uuDsT64QmoNji/d18UwRitPSpBkyUXwaGKcct/QCT82206p+zcXJfbWZ9dWL X61X6t7/X5r6xmi7bBbZEb7XEm4VICmJYbVIuQko= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from [10.206.24.124] (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sayalil@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id B330B606FA; Thu, 9 Aug 2018 08:50:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1533804631; bh=bmTsXFgWnM32PaUKbXlD+i/H5+ixoWxvafxcJ7mubus=; h=Subject:To:Cc:References:From:Date:In-Reply-To:From; b=C4Ohh0AulA/O/U8pGf0XdFpeMrB6p6IvS7xq7l0wnAPy3XpUbYeL9uksnEtR6gqy5 JPMHYBy83idE5vVqwQUz5BEBQSXaTnJKEN0eE6daaOVwavDMTHqhPZBa5qSUUdLumY nYKA8FDBtN82YNWtN3C6BHvX2j6OC7Kxo6ItiZAU= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org B330B606FA Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sayalil@codeaurora.org Subject: Re: [PATCH V7 1/2] scsi: ufs: set the device reference clock setting To: Evan Green Cc: subhashj@codeaurora.org, cang@codeaurora.org, vivek.gautam@codeaurora.org, Rajendra Nayak , Vinayak Holikatti , jejb@linux.vnet.ibm.com, martin.petersen@oracle.com, asutoshd@codeaurora.org, riteshh@codeaurora.org, adrian.hunter@intel.com, linux-scsi@vger.kernel.org, linux-kernel@vger.kernel.org References: <1533113338-31750-1-git-send-email-sayalil@codeaurora.org> <1533113338-31750-2-git-send-email-sayalil@codeaurora.org> From: Sayali Lokhande Message-ID: Date: Thu, 9 Aug 2018 14:20:25 +0530 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Evan, On 8/6/2018 10:56 PM, Evan Green wrote: > Hi Sayali, > > On Wed, Aug 1, 2018 at 1:49 AM Sayali Lokhande wrote: >> From: Subhash Jadavani >> >> UFS host supplies the reference clock to UFS device and UFS device >> specification allows host to provide one of the 4 frequencies (19.2 MHz, >> 26 MHz, 38.4 MHz, 52 MHz) for reference clock. Host should set the >> device reference clock frequency setting in the device based on what >> frequency it is supplying to UFS device. >> >> Signed-off-by: Subhash Jadavani >> Signed-off-by: Can Guo >> Signed-off-by: Sayali Lokhande >> --- >> drivers/scsi/ufs/ufs.h | 8 ++++ >> drivers/scsi/ufs/ufshcd-pltfrm.c | 2 + >> drivers/scsi/ufs/ufshcd.c | 84 ++++++++++++++++++++++++++++++++++++++++ >> drivers/scsi/ufs/ufshcd.h | 2 + >> 4 files changed, 96 insertions(+) >> >> diff --git a/drivers/scsi/ufs/ufs.h b/drivers/scsi/ufs/ufs.h >> index 14e5bf7..89e0a33 100644 >> --- a/drivers/scsi/ufs/ufs.h >> +++ b/drivers/scsi/ufs/ufs.h >> @@ -378,6 +378,14 @@ enum query_opcode { >> UPIU_QUERY_OPCODE_TOGGLE_FLAG = 0x8, >> }; >> >> +/* bRefClkFreq attribute values */ >> +enum ref_clk_freq { >> + REF_CLK_FREQ_19_2_MHZ = 19200000, >> + REF_CLK_FREQ_26_MHZ = 26000000, >> + REF_CLK_FREQ_38_4_MHZ = 38400000, >> + REF_CLK_FREQ_52_MHZ = 52000000, >> +}; >> + >> /* Query response result code */ >> enum { >> QUERY_RESULT_SUCCESS = 0x00, >> diff --git a/drivers/scsi/ufs/ufshcd-pltfrm.c b/drivers/scsi/ufs/ufshcd-pltfrm.c >> index e82bde0..0953563 100644 >> --- a/drivers/scsi/ufs/ufshcd-pltfrm.c >> +++ b/drivers/scsi/ufs/ufshcd-pltfrm.c >> @@ -343,6 +343,8 @@ int ufshcd_pltfrm_init(struct platform_device *pdev, >> pm_runtime_set_active(&pdev->dev); >> pm_runtime_enable(&pdev->dev); >> >> + ufshcd_parse_dev_ref_clk_freq(hba); >> + >> ufshcd_init_lanes_per_dir(hba); >> >> err = ufshcd_init(hba, mmio_base, irq); >> diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c >> index c5b1bf1..619313b 100644 >> --- a/drivers/scsi/ufs/ufshcd.c >> +++ b/drivers/scsi/ufs/ufshcd.c >> @@ -6296,6 +6296,84 @@ static void ufshcd_def_desc_sizes(struct ufs_hba *hba) >> hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE; >> } >> >> +void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba) >> +{ >> + struct device *dev = hba->dev; >> + struct device_node *np = dev->of_node; >> + struct clk *refclk = NULL; >> + >> + if (!np) >> + return; >> + >> + refclk = of_clk_get_by_name(np, "ref_clk"); >> + if (refclk) >> + hba->dev_ref_clk_freq = clk_get_rate(refclk); >> + else if (!refclk || >> + (hba->dev_ref_clk_freq > REF_CLK_FREQ_52_MHZ)) { > What is this logic? The !refclk condition will always be true since > you're in the else case of if (refclk). Also, even if the second part > were executed somehow, you haven't assigned dev_ref_clk_freq yet, so > how can its value be anything other than 0? Maybe that whole > conditional was just not supposed to be an "else" at all, but a > standalone if? Agree. Will update. >> + dev_err(hba->dev, >> + "%s: invalid ref_clk setting = %u\n", >> + __func__, hba->dev_ref_clk_freq); > There's probably no need to complain if the clock simply couldn't be > found, only if an unexpected value was found. Agree. Will update. >> + hba->dev_ref_clk_freq = 0; >> + } >> +} >> + >> +static int ufshcd_set_dev_ref_clk(struct ufs_hba *hba) >> +{ >> + int err = 0; >> + int ref_clk = -1; >> + static const char * const ref_clk_freqs[] = {"19.2 MHz", "26 MHz", >> + "38.4 MHz", "52 MHz"}; >> + >> + err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, >> + QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &ref_clk); >> + >> + if (err) { >> + dev_err(hba->dev, "%s: failed reading bRefClkFreq. err = %d\n", >> + __func__, err); >> + goto out; >> + } >> + >> + switch (hba->dev_ref_clk_freq) { >> + case REF_CLK_FREQ_19_2_MHZ: >> + hba->dev_ref_clk_freq = 0x0; >> + break; >> + case REF_CLK_FREQ_26_MHZ: >> + hba->dev_ref_clk_freq = 0x1; >> + break; >> + case REF_CLK_FREQ_38_4_MHZ: >> + hba->dev_ref_clk_freq = 0x2; >> + break; >> + case REF_CLK_FREQ_52_MHZ: >> + hba->dev_ref_clk_freq = 0x3; >> + break; >> + default: >> + dev_err(hba->dev, >> + "%s: invalid ref_clk setting = %u\n", >> + __func__, hba->dev_ref_clk_freq); >> + goto out; >> + } > Please don't assign two different things (frequency in Hertz and > bref_clk value) into the same structure member. > > I think rather than having this switch statement you should iterate > through a table that contains elements of {freq_hz, bref_clk, string}. > I think you should do this up in ufshcd_parse_dev_ref_clk_freq so that > you don't have to redo that calculation on every rescan. Then store > the final bRefClkFreq value (or -1 if no definitive answer could be > reached) in your new structure member. Then all this function does is > 1) Nothing if dev_ref_clk_freq is -1, or 2) read and maybe write the > attribute. Agree. Will update. >> + >> + if (ref_clk == hba->dev_ref_clk_freq) >> + goto out; /* nothing to update */ >> + >> + err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, >> + QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, >> + &hba->dev_ref_clk_freq); >> + >> + if (err) >> + dev_err(hba->dev, "%s: bRefClkFreq setting to %s failed\n", >> + __func__, ref_clk_freqs[hba->dev_ref_clk_freq]); >> + /* >> + * It is good to print this out here to debug any later failures >> + * related to gear switch. >> + */ >> + dev_dbg(hba->dev, "%s: bRefClkFreq setting to %s succeeded\n", >> + __func__, ref_clk_freqs[hba->dev_ref_clk_freq]); >> + >> +out: >> + return err; >> +} >> + >> /** >> * ufshcd_probe_hba - probe hba to detect device and initialize >> * @hba: per-adapter instance >> @@ -6361,6 +6439,12 @@ static int ufshcd_probe_hba(struct ufs_hba *hba) >> "%s: Failed getting max supported power mode\n", >> __func__); >> } else { >> + /* >> + * Set the right value to bRefClkFreq before attempting to >> + * switch to HS gears. >> + */ >> + if (hba->dev_ref_clk_freq) >> + ufshcd_set_dev_ref_clk(hba); >> ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info); >> if (ret) { >> dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n", >> diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h >> index 8110dcd..101a75c 100644 >> --- a/drivers/scsi/ufs/ufshcd.h >> +++ b/drivers/scsi/ufs/ufshcd.h >> @@ -548,6 +548,7 @@ struct ufs_hba { >> void *priv; >> unsigned int irq; >> bool is_irq_enabled; >> + u32 dev_ref_clk_freq; > If you followed my suggestion of this storing _only_ the bRefClkFreq > value or -1 if unset, then this would need to be signed, and > initialized somewhere so that 0 wasn't accidentally taken to be a > parsed value. Will check and update (if necessary). >> /* Interrupt aggregation support is broken */ >> #define UFSHCD_QUIRK_BROKEN_INTR_AGGR 0x1 >> @@ -746,6 +747,7 @@ static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg) >> int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask, >> u32 val, unsigned long interval_us, >> unsigned long timeout_ms, bool can_sleep); >> +void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba); >> >> static inline void check_upiu_size(void) >> { >> -- >> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, >> a Linux Foundation Collaborative Project >>