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[209.132.180.67]) by mx.google.com with ESMTP id d8-v6si6203238pgn.382.2018.08.09.04.46.13; Thu, 09 Aug 2018 04:46:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730889AbeHIOJy (ORCPT + 99 others); Thu, 9 Aug 2018 10:09:54 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:13485 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727768AbeHIOJy (ORCPT ); Thu, 9 Aug 2018 10:09:54 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1, AES128-SHA) id ; Thu, 09 Aug 2018 04:45:10 -0700 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 09 Aug 2018 04:45:23 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 09 Aug 2018 04:45:23 -0700 Received: from dhcp-10-21-25-168 (10.21.25.201) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 9 Aug 2018 11:45:20 +0000 Date: Thu, 9 Aug 2018 14:45:15 +0300 From: Aapo Vienamo To: Thierry Reding CC: Ulf Hansson , Rob Herring , Mark Rutland , Jonathan Hunter , Adrian Hunter , "Mikko Perttunen" , , , , Subject: Re: [PATCH 1/8] dt-bindings: mmc: Add DQS trim value to Tegra SDHCI Message-ID: <20180809144515.06089abe@dhcp-10-21-25-168> In-Reply-To: <20180809113609.GI21639@ulmo> References: <1533650404-18125-1-git-send-email-avienamo@nvidia.com> <1533650404-18125-2-git-send-email-avienamo@nvidia.com> <20180809113609.GI21639@ulmo> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.21.25.201] X-ClientProxiedBy: UKMAIL101.nvidia.com (10.26.138.13) To HQMAIL101.nvidia.com (172.20.187.10) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 9 Aug 2018 13:36:09 +0200 Thierry Reding wrote: > On Tue, Aug 07, 2018 at 04:59:57PM +0300, Aapo Vienamo wrote: > > Document HS400 DQS trim value device tree property. > > > > Signed-off-by: Aapo Vienamo > > --- > > Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt > > index 3c7960a..7d294f3 100644 > > --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt > > +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt > > @@ -72,6 +72,7 @@ Optional properties for Tegra210 and Tegra186: > > trimmer value for non-tunable modes. > > - nvidia,default-trim : Specify the default outbound clock trimmer > > value. > > +- nvidia,dqs-trim : Specify DQS trim value for HS400 timing > > > > Notes on the pad calibration pull up and pulldown offset values: > > - The property values are drive codes which are programmed into the > > @@ -88,6 +89,8 @@ Optional properties for Tegra210 and Tegra186: > > - The values are programmed to the Vendor Clock Control Register. > > Please refer to the reference manual of the SoC for correct > > values. > > + - The DQS trim values are only used on controllers which support > > + HS400 timing. > > One of these additions says "DQS trim values", the other says "DQS trim > value". It is unclear from the above how many values there are. I think > this should be more explicit. Also, I don't see why the note about which > controllers the DQS trim value(s) applies to is in a separate paragraph. > Couldn't it be moved to the property description? It's a single value. The plural form is a mistake. > Also, I think the bindings should specify which generations of Tegra do > support HS400. Where else are people supposed to find that information? This property is under the "Optional properties for Tegra210 and Tegra186" section and it only applies for the said generations. -Aapo