Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
MIME-Version: 1.0
References: <1533223316-9942-1-git-send-email-zong@andestech.com> <3AB16BFE6992A349B44EA6D8F29BFB476B1EA2CC@ATCPCS16.andestech.com>
In-Reply-To: <3AB16BFE6992A349B44EA6D8F29BFB476B1EA2CC@ATCPCS16.andestech.com>
From:   Zong Li <zongbox@gmail.com>
Date:   Fri, 10 Aug 2018 08:37:39 +0800
Message-ID: <CA+ZOyajyOfjZh8tQB4reAka3s+tqXachY4hiAtpA4Bb67x58AQ@mail.gmail.com>
Subject: Re: FW: [PATCH v2] RISC-V: Add the directive for alignment of stvec's value
To:     Palmer Dabbelt <palmer@sifive.com>, aou@eecs.berkeley.edu,
        hch@infradead.org, linux-riscv@lists.infradead.org,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Zong Li <zong@andestech.com>, greentime@adnestech.com
Content-Type: text/plain; charset="UTF-8"
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

> Subject: [PATCH v2] RISC-V: Add the directive for alignment of stvec's value
>
> The stvec's value must be 4 byte alignment by specification definition.
> These directives avoid to stvec be set the non-alignment value.
>
> Signed-off-by: Zong Li <zong@andestech.com>
> ---
>  arch/riscv/kernel/head.S | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 3b6293f..11066d5 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -94,6 +94,7 @@ relocate:
>         or a0, a0, a1
>         sfence.vma
>         csrw sptbr, a0
> +.align 2
>  1:
>         /* Set trap vector to spin forever to help debug */
>         la a0, .Lsecondary_park
> @@ -143,6 +144,7 @@ relocate:
>         tail smp_callin
>  #endif
>
> +.align 2
>  .Lsecondary_park:
>         /* We lack SMP support or have too many harts, so park this hart */
>         wfi


ping