Received: by 2002:ac0:a5a7:0:0:0:0:0 with SMTP id m36-v6csp301538imm; Fri, 10 Aug 2018 11:30:01 -0700 (PDT) X-Google-Smtp-Source: AA+uWPxQXu63QlanI/0OoQK652EHtiVr/1WA/2ibjZ3RFULPLNNIxqieq71Wd29du+xgZbjX3RVb X-Received: by 2002:a62:e30c:: with SMTP id g12-v6mr8154989pfh.25.1533925801503; Fri, 10 Aug 2018 11:30:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533925801; cv=none; d=google.com; s=arc-20160816; b=yGveRDJITKX9Q3mBGnflXfJ04Q0jX7vO90h5d9hLmjOazEP0OB1MQ0k2HNsNIwdK7O u10G74IJ5ViMenQG3lT9YUb4JERNB04I09/XKR3vxLdSrv1rGXstONrUqoyjugR59CEr I45NaoHLKUArMQePT2XqthboKUsZwH/f6B/iBd1+pGY8K7U+GsFyb7RZ33l1RH9piWqV iHd8eTEQYi9bw7eq6aekkC/wCZ1XAXzN95YknFb+oFjK+eRPV7ko9Cz9jgT01VLxlYwr OOsA0qHlkRy4iIfJ07fWs+JJ6Gztv+2f83Q4RFShB5wW38VG8Xyq8R5MTQdZb1WL7iL/ OdEA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=Uy7L8mbQAlaqaHgsIyDzJK1BM/tJZKqHdgNEx7UpUck=; b=XW1ReX/yQWD5Bs4FM5+Of3cxk0XM9tCzDUNRlE/vQEcxriZhBVyoJp1sqrRffXy0f9 zPu5cyoDc01qDdtmvHi9SeVPRxfIDp8r/dnx0b5FaM7LhwkFpYN0v6nNyrGxExX0wo+W oW3RsdfDT7FC+J6vSN58DwLYAASe/qVwnkeOr7ra0QcPUYVv7uqu7vHPZ7x/1OMfhL1v woahtM+hshNxaN2CTOYbHljOtCQQI0px5rrJcps49Ex7bqzrSTzIsnqHB63kgL59Nl5f VkgG0Vr7v7aECpWDdy/A0v0ULnhisv8SSTVKJiFxgXCmvNuvbF4QSvMrPGSsDCUeMWwt t/4Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id cd4-v6si8467122plb.516.2018.08.10.11.29.47; Fri, 10 Aug 2018 11:30:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729599AbeHJUj6 (ORCPT + 99 others); Fri, 10 Aug 2018 16:39:58 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:19008 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728185AbeHJUj4 (ORCPT ); Fri, 10 Aug 2018 16:39:56 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1, AES128-SHA) id ; Fri, 10 Aug 2018 11:08:46 -0700 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 10 Aug 2018 11:09:01 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 10 Aug 2018 11:09:01 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Fri, 10 Aug 2018 18:09:00 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Fri, 10 Aug 2018 18:09:00 +0000 Received: from dhcp-10-21-25-168.Nvidia.com (Not Verified[10.21.25.201]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 10 Aug 2018 11:09:00 -0700 From: Aapo Vienamo To: Rob Herring , Mark Rutland , Thierry Reding , Jonathan Hunter , Ulf Hansson , Adrian Hunter , Mikko Perttunen , Stefan Agner CC: , , , , Aapo Vienamo Subject: [PATCH v2 04/40] dt-bindings: mmc: Add Tegra SDHCI sampling trimmer values Date: Fri, 10 Aug 2018 21:08:06 +0300 Message-ID: <1533924522-1037-5-git-send-email-avienamo@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533924522-1037-1-git-send-email-avienamo@nvidia.com> References: <1533924522-1037-1-git-send-email-avienamo@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Document the Tegra SDHCI inbound and outbound sampling trimmer values. Signed-off-by: Aapo Vienamo --- .../devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt index 9713e05..edecf97 100644 --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt @@ -67,6 +67,10 @@ Optional properties for Tegra210 and Tegra186: - nvidia,pad-autocal-pull-up-offset-hs400, nvidia,pad-autocal-pull-down-offset-hs400 : Specify drive strength calibration offsets for HS400 mode. +- nvidia,default-tap : Specify the default inbound sampling clock + trimmer value for non-tunable modes. +- nvidia,default-trim : Specify the default outbound clock trimmer + value. Notes on the pad calibration pull up and pulldown offset values: - The property values are drive codes which are programmed into the @@ -77,6 +81,13 @@ Optional properties for Tegra210 and Tegra186: - The SDR104 and HS400 timing specific values are used in corresponding modes if specified. + Notes on tap and trim values: + - The values are used for compensating trace length differences + by adjusting the sampling point. + - The values are programmed to the Vendor Clock Control Register. + Please refer to the reference manual of the SoC for correct + values. + Example: sdhci@700b0000 { compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; -- 2.7.4