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Date:   Tue, 14 Aug 2018 08:49:53 +0200
From:   Quentin Schulz <quentin.schulz@bootlin.com>
To:     Rob Herring <robh@kernel.org>
Cc:     alexandre.belloni@bootlin.com, ralf@linux-mips.org,
        paul.burton@mips.com, jhogan@kernel.org, mark.rutland@arm.com,
        davem@davemloft.net, kishon@ti.com, andrew@lunn.ch,
        f.fainelli@gmail.com, linux-mips@linux-mips.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        netdev@vger.kernel.org, allan.nielsen@microsemi.com,
        thomas.petazzoni@bootlin.com
Subject: Re: [PATCH net-next 02/10] dt-bindings: net: ocelot: remove hsio
 from the list of register address spaces
Message-ID: <20180814064953.vboz2gryq4jff34n@qschulz>
References: <cover.aa759035f6eefdd0bb2a5ae335dab5bd5399bd46.1532954208.git-series.quentin.schulz@bootlin.com>
 <3558e538b55a2249b0a179c04c27e9d3715bbbaa.1532954208.git-series.quentin.schulz@bootlin.com>
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Hi Rob,

On Mon, Aug 13, 2018 at 04:31:03PM -0600, Rob Herring wrote:
> On Mon, Jul 30, 2018 at 02:43:47PM +0200, Quentin Schulz wrote:
> > HSIO register address space should be handled outside of the MAC
> > controller as there are some registers for PLL5 configuring,
> > SerDes/switch port muxing and a thermal sensor IP, so let's remove it.
> >=20
> > Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
> > ---
> >  Documentation/devicetree/bindings/mips/mscc.txt       | 16 +++++++++++=
+-
> >  Documentation/devicetree/bindings/net/mscc-ocelot.txt |  9 ++-----
> >  2 files changed, 19 insertions(+), 6 deletions(-)
> >=20
> > diff --git a/Documentation/devicetree/bindings/mips/mscc.txt b/Document=
ation/devicetree/bindings/mips/mscc.txt
> > index ae15ec3..bc817e9 100644
> > --- a/Documentation/devicetree/bindings/mips/mscc.txt
> > +++ b/Documentation/devicetree/bindings/mips/mscc.txt
> > @@ -41,3 +41,19 @@ Example:
> >  		compatible =3D "mscc,ocelot-cpu-syscon", "syscon";
> >  		reg =3D <0x70000000 0x2c>;
> >  	};
> > +
> > +o HSIO regs:
> > +
> > +The SoC has a few registers (HSIO) handling miscellaneous functionalit=
ies:
> > +configuration and status of PLL5, RCOMP, SyncE, SerDes configurations =
and
> > +status, SerDes muxing and a thermal sensor.
> > +
> > +Required properties:
> > +- compatible: Should be "mscc,ocelot-hsio", "syscon", "simple-mfd"
> > +- reg : Should contain registers location and length
> > +
> > +Example:
> > +	syscon@10d0000 {
> > +		compatible =3D "mscc,ocelot-hsio", "syscon", "simple-mfd";
>=20
> simple-mfd is not appropriate without child nodes, so drop it.
>=20

Understood but it's an intermediate patch. Later (patch 8), the SerDes
muxing "controller" is added as a child to this node. There most likely
will be some others in the future (temperature sensor for example).

Furthermore, there's already a simple-mfd without children in this file:
https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bin=
dings/mips/mscc.txt#L19

How should we handle this case?

Thanks,
Quentin

> > +		reg =3D <0x10d0000 0x10000>;
> > +	};
> > diff --git a/Documentation/devicetree/bindings/net/mscc-ocelot.txt b/Do=
cumentation/devicetree/bindings/net/mscc-ocelot.txt
> > index 0a84711..9e5c17d 100644
> > --- a/Documentation/devicetree/bindings/net/mscc-ocelot.txt
> > +++ b/Documentation/devicetree/bindings/net/mscc-ocelot.txt
> > @@ -12,7 +12,6 @@ Required properties:
> >    - "sys"
> >    - "rew"
> >    - "qs"
> > -  - "hsio"
> >    - "qsys"
> >    - "ana"
> >    - "portX" with X from 0 to the number of last port index available o=
n that
> > @@ -45,7 +44,6 @@ Example:
> >  		reg =3D <0x1010000 0x10000>,
> >  		      <0x1030000 0x10000>,
> >  		      <0x1080000 0x100>,
> > -		      <0x10d0000 0x10000>,
> >  		      <0x11e0000 0x100>,
> >  		      <0x11f0000 0x100>,
> >  		      <0x1200000 0x100>,
> > @@ -59,10 +57,9 @@ Example:
> >  		      <0x1280000 0x100>,
> >  		      <0x1800000 0x80000>,
> >  		      <0x1880000 0x10000>;
> > -		reg-names =3D "sys", "rew", "qs", "hsio", "port0",
> > -			    "port1", "port2", "port3", "port4", "port5",
> > -			    "port6", "port7", "port8", "port9", "port10",
> > -			    "qsys", "ana";
> > +		reg-names =3D "sys", "rew", "qs", "port0", "port1", "port2",
> > +			    "port3", "port4", "port5", "port6", "port7",
> > +			    "port8", "port9", "port10", "qsys", "ana";
> >  		interrupts =3D <21 22>;
> >  		interrupt-names =3D "xtr", "inj";
> > =20
> > --=20
> > git-series 0.9.1

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