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[209.132.180.67]) by mx.google.com with ESMTP id z37-v6si19032389pgl.390.2018.08.14.05.16.39; Tue, 14 Aug 2018 05:16:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=GM5pPE9e; dkim=pass header.i=@codeaurora.org header.s=default header.b=BIDNe4vP; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732538AbeHNPBa (ORCPT + 99 others); Tue, 14 Aug 2018 11:01:30 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:43502 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731879AbeHNPBa (ORCPT ); Tue, 14 Aug 2018 11:01:30 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 257E460DD4; Tue, 14 Aug 2018 12:14:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1534248875; bh=ldc0WMWvlds2EQ7RCkF8xSmUH8Hk8lJKEZbeIrOigFw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GM5pPE9e+jSbUM0NWA6Id7cSLEijmGUUu/yHobC/dCJXUo2pQlL88Prc2UEYEegC1 DSRK82iENWrq70M2wXKbcGvY+cEqEhmdlAEAkSfrcjjSLjuxLnheZUGNLhJEGLEQq5 2cvKewUnneEsoEHWjqCupB1tWtyGkRH1EwbZbpJQ= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from srichara-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sricharan@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id D3CAF60D82; Tue, 14 Aug 2018 12:14:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1534248856; bh=ldc0WMWvlds2EQ7RCkF8xSmUH8Hk8lJKEZbeIrOigFw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BIDNe4vPhElH5GsO/7p3d18z9EgBF8kc6qLHFrIC0lALQaa9NfGuFNCLNtFFaxyZx 6HPZQ5TL7AJzW1TYAULqP67v4y/H/nuAF0YOFvViFRxsNcsb2zi6+edJV1XSQrebR7 +E59kZsz8phpj+bAnSpTVGlgAX4wmGeuYyoKCT4k= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org D3CAF60D82 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sricharan@codeaurora.org From: Sricharan R To: mark.rutland@arm.com, robh@kernel.org, sudeep.holla@arm.com, linux@arm.linux.org.uk, ctatlor97@gmail.com, rjw@rjwysocki.net, viresh.kumar@linaro.org, mturquette@baylibre.com, linux-pm@vger.kernel.org, sboyd@codeaurora.org, linux@armlinux.org.uk, thierry.escande@linaro.org, linux-kernel@vger.kernel.org, david.brown@linaro.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, andy.gross@linaro.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, niklas.cassel@linaro.org Cc: sricharan@codeaurora.org Subject: [PATCH v12 12/14] clk: qcom: Add safe switch hook for krait mux clocks Date: Tue, 14 Aug 2018 17:42:31 +0530 Message-Id: <1534248753-2440-13-git-send-email-sricharan@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1534248753-2440-1-git-send-email-sricharan@codeaurora.org> References: <1534248753-2440-1-git-send-email-sricharan@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When the Hfplls are reprogrammed during the rate change, the primary muxes which are sourced from the same hfpll for higher frequencies, needs to be switched to the 'safe secondary mux' as the parent for that small window. This is done by registering a clk notifier for the muxes and switching to the safe parent in the PRE_RATE_CHANGE notifier and back to the original parent in the POST_RATE_CHANGE notifier. Signed-off-by: Sricharan R --- drivers/clk/qcom/clk-krait.c | 2 ++ drivers/clk/qcom/clk-krait.h | 3 +++ drivers/clk/qcom/krait-cc.c | 56 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 61 insertions(+) diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c index 7ede744..59f1af4 100644 --- a/drivers/clk/qcom/clk-krait.c +++ b/drivers/clk/qcom/clk-krait.c @@ -50,6 +50,8 @@ static int krait_mux_set_parent(struct clk_hw *hw, u8 index) if (__clk_is_enabled(hw->clk)) __krait_mux_set_sel(mux, sel); + mux->reparent = true; + return 0; } diff --git a/drivers/clk/qcom/clk-krait.h b/drivers/clk/qcom/clk-krait.h index 441ba1e..9120bd2 100644 --- a/drivers/clk/qcom/clk-krait.h +++ b/drivers/clk/qcom/clk-krait.h @@ -12,6 +12,9 @@ struct krait_mux_clk { u32 shift; u32 en_mask; bool lpl; + u8 safe_sel; + u8 old_index; + bool reparent; struct clk_hw hw; struct notifier_block clk_nb; diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c index 7c9dfb0..4d4b657 100644 --- a/drivers/clk/qcom/krait-cc.c +++ b/drivers/clk/qcom/krait-cc.c @@ -26,6 +26,49 @@ 0, }; +/* + * Notifier function for switching the muxes to safe parent + * while the hfpll is getting reprogrammed. + */ +static int krait_notifier_cb(struct notifier_block *nb, + unsigned long event, + void *data) +{ + int ret = 0; + struct krait_mux_clk *mux = container_of(nb, struct krait_mux_clk, + clk_nb); + /* Switch to safe parent */ + if (event == PRE_RATE_CHANGE) { + mux->old_index = krait_mux_clk_ops.get_parent(&mux->hw); + ret = krait_mux_clk_ops.set_parent(&mux->hw, mux->safe_sel); + mux->reparent = false; + /* + * By the time POST_RATE_CHANGE notifier is called, + * clk framework itself would have changed the parent for the new rate. + * Only otherwise, put back to the old parent. + */ + } else if (event == POST_RATE_CHANGE) { + if (!mux->reparent) + ret = krait_mux_clk_ops.set_parent(&mux->hw, + mux->old_index); + } + + return notifier_from_errno(ret); +} + +static int krait_notifier_register(struct device *dev, struct clk *clk, + struct krait_mux_clk *mux) +{ + int ret = 0; + + mux->clk_nb.notifier_call = krait_notifier_cb; + ret = clk_notifier_register(clk, &mux->clk_nb); + if (ret) + dev_err(dev, "failed to register clock notifier: %d\n", ret); + + return ret; +} + static int krait_add_div(struct device *dev, int id, const char *s, unsigned int offset) { @@ -70,6 +113,7 @@ krait_add_sec_mux(struct device *dev, int id, const char *s, unsigned int offset, bool unique_aux) { + int ret; struct krait_mux_clk *mux; static const char *sec_mux_list[] = { "acpu_aux", @@ -93,6 +137,7 @@ mux->shift = 2; mux->parent_map = sec_mux_map; mux->hw.init = &init; + mux->safe_sel = 0; init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); if (!init.name) @@ -108,6 +153,11 @@ clk = devm_clk_register(dev, &mux->hw); + ret = krait_notifier_register(dev, clk, mux); + if (ret) + goto unique_aux; + +unique_aux: if (unique_aux) kfree(sec_mux_list[0]); err_aux: @@ -119,6 +169,7 @@ krait_add_pri_mux(struct device *dev, int id, const char *s, unsigned int offset) { + int ret; struct krait_mux_clk *mux; const char *p_names[3]; struct clk_init_data init = { @@ -139,6 +190,7 @@ mux->lpl = id >= 0; mux->parent_map = pri_mux_map; mux->hw.init = &init; + mux->safe_sel = 2; init.name = kasprintf(GFP_KERNEL, "krait%s_pri_mux", s); if (!init.name) @@ -164,6 +216,10 @@ clk = devm_clk_register(dev, &mux->hw); + ret = krait_notifier_register(dev, clk, mux); + if (ret) + goto err_p3; +err_p3: kfree(p_names[2]); err_p2: kfree(p_names[1]); -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation