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[209.132.180.67]) by mx.google.com with ESMTP id o123-v6si24318056pgo.190.2018.08.15.08.29.24; Wed, 15 Aug 2018 08:29:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b="e6XsM/wR"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729577AbeHOSUk (ORCPT + 99 others); Wed, 15 Aug 2018 14:20:40 -0400 Received: from mail-pl0-f68.google.com ([209.85.160.68]:37364 "EHLO mail-pl0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729311AbeHOSUk (ORCPT ); Wed, 15 Aug 2018 14:20:40 -0400 Received: by mail-pl0-f68.google.com with SMTP id d5-v6so608946pll.4 for ; Wed, 15 Aug 2018 08:28:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=mime-version:content-transfer-encoding:to:from:in-reply-to:cc :references:message-id:user-agent:subject:date; bh=rnTzvgA36ckKe0nn6tIRwKJTxndspYTB4aAIi0BI1q0=; b=e6XsM/wRKt3DEA1MLk1YYG1CSYEcLkdWgXVJs/+boYVVYpbEjgkVBq809jlRgdyjr5 dnNDvGg0VrLfF1zD/rw3xlRwc1C3Wn9mFY061ctNWF9avAJgFJWYpOcA0gG1PuOM10il InKGdS+1wH/r7Gpc/mbvBXW7KolWHGtdxaiB8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:content-transfer-encoding:to:from :in-reply-to:cc:references:message-id:user-agent:subject:date; bh=rnTzvgA36ckKe0nn6tIRwKJTxndspYTB4aAIi0BI1q0=; b=Q8OTFkCRfpt8Hc+x8RuNcxo50tM/LU8lz8XyF4GFmFzb8CX46R7YYjEk48357pUlMe fNuh+rKCS3FnfgSriRmUcXTmtaLqFnd1u8sD+7UQSIlAr++JACEgX9SoUUXWYWcPQnSY TRvQqeeIdHkpLoLSMGBlTZD5sa+5zql0zeivsXner3KLbp25aUw5yoUru4InY0wW2lEg bSgLXXvK9Vp7p2bNOxBmXox5djhheUoz8gpZ8PPF6WWJ4I0iHL65KMe/LOn2S3mQapLB HWT6RC0AcklWQrCYw1aVDnLDtf1e+RkGEuGZE0Mz8vWr5UMYPLk11N1bleEQmVeU8Z7o GG5A== X-Gm-Message-State: AOUpUlFp/1QwxZpdAVbld7cF1Eo5cDnKMJCMpdR7cPvORKsyEtEbRSLE +5IdU+NfylGx61Ph/SRJh/Qtrg== X-Received: by 2002:a17:902:82c7:: with SMTP id u7-v6mr24706301plz.83.1534346884148; Wed, 15 Aug 2018 08:28:04 -0700 (PDT) Received: from localhost ([2620:15c:202:201:7e28:b9f3:6afc:5326]) by smtp.gmail.com with ESMTPSA id x25-v6sm22145041pgv.63.2018.08.15.08.28.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 15 Aug 2018 08:28:03 -0700 (PDT) Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: Lina Iyer , andy.gross@linaro.org, bjorn.andersson@linaro.org From: Stephen Boyd In-Reply-To: <20180814173058.26143-1-ilina@codeaurora.org> Cc: marc.zyngier@arm.com, rplsssn@codeaurora.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, rnayak@codeaurora.org, devicetree@vger.kernel.org, david.brown@linaro.org, evgreen@chromium.org, dianders@chromium.org, Lina Iyer References: <20180814173058.26143-1-ilina@codeaurora.org> Message-ID: <153434688280.37448.5200368407995060713@swboyd.mtv.corp.google.com> User-Agent: alot/0.7 Subject: Re: [PATCH] arm64: dts: msm: add PDC device bindings for sdm845 Date: Wed, 15 Aug 2018 08:28:02 -0700 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Quoting Lina Iyer (2018-08-14 10:30:58) > Add PDC interrupt controller device bindings for SDM845. > = > Signed-off-by: Lina Iyer > --- > arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +++++++++ > 1 file changed, 9 insertions(+) > = > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/q= com/sdm845.dtsi > index 24e254efb9d1..399bfbd52c5b 100644 > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > @@ -1106,6 +1106,15 @@ > }; > }; > = > + pdc: interrupt-controller@b220000 { Please sort this by unit address within the SoC node. > + compatible =3D "qcom,sdm845-pdc"; > + reg =3D <0xb220000 0x30000>; > + qcom,pdc-ranges =3D <0 512 94>, <94 641 15>, <115= 662 7>; > + #interrupt-cells =3D <2>; > + interrupt-parent =3D <&intc>; > + interrupt-controller; > + }; > + > timer@17c90000 { > #address-cells =3D <1>; > #size-cells =3D <1>;