To: linux-kernel@vger.kernel.org
Path: gatekeeper.tmr.com!davidsen
From: davidsen@tmr.com (bill davidsen)
Newsgroups: mail.linux-kernel
Subject: Re: [PATCH] Athlon Prefetch workaround for 2.6.0test6
Date: 29 Sep 2003 21:02:39 GMT
Organization: TMR Associates, Schenectady NY
Lines: 26
Message-ID: <bla6lf$3ul$1@gatekeeper.tmr.com>
References: <20030929125629.GA1746@averell>
Originator: davidsen@gatekeeper.tmr.com
Sender: linux-kernel-owner@vger.kernel.org

In article <20030929125629.GA1746@averell>, Andi Kleen  <ak@muc.de> wrote:

| It removes the previous dumb in kernel workaround for this and shrinks the 
| kernel by >10k.
| 
| Small behaviour change is that a SIGBUS fault for a *_user access will
| cause an EFAULT now, no SIGBUS.
| 
| This version addresses all criticism that I got for previous versions.
| 
| - Only checks on AMD K7+ CPUs. 
| - Computes linear address for VM86 mode or code segments
| with non zero base.
| - Some cleanup
| - No pointer comparisons
| - More comments

I have to try this on a P4 and K7, but WRT "Only checks on AMD K7+ CPUs"
I hope you meant "only generates code if AMD CPU is target" and not that
the code size penalty is still there for CPUs which don't need it.

Will check Wednesday, life is very busy right now.
-- 
bill davidsen <davidsen@tmr.com>
  CTO, TMR Associates, Inc
Doing interesting things with little computers since 1979.
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