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[209.132.180.67]) by mx.google.com with ESMTP id w25-v6si13738966pfa.359.2018.08.21.10.09.37; Tue, 21 Aug 2018 10:09:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@brainfault-org.20150623.gappssmtp.com header.s=20150623 header.b=Vld+L0Jx; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727020AbeHUUZi (ORCPT + 99 others); Tue, 21 Aug 2018 16:25:38 -0400 Received: from mail-wr1-f68.google.com ([209.85.221.68]:38740 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726609AbeHUUZi (ORCPT ); Tue, 21 Aug 2018 16:25:38 -0400 Received: by mail-wr1-f68.google.com with SMTP id w11-v6so13898555wrc.5 for ; Tue, 21 Aug 2018 10:04:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=FKzjo54RIPB2NUwiG8mqiZqKdVRLyqbjaLowygDU56k=; b=Vld+L0JxZxo+mrq0OvOJj9avcJSX2GthVC6gqtZ+S1gh8TgTZLsW6FFO7KfscUZSbL vRg2GgRGeLG0+vmSjoG2DvxMeuHRzZhU++aVyj6kKDwWHFjOUm2nNioNWuYJSeVNM+oM gKrY5lZsRCbNA92GJ5B4QB9BJCgspBp9JIizPJio0tvEzZ6MEmIpOqojoXWy9KG8R4+0 Pqh8A0y1kRhHh0DtJ91GZo/qfUp7ryHYwURMGBuipPEK/ijozloaQSr2pS8JZj+2TYlC iSpjrJu7yfj6jh5EqdH6X+ZHrSezhCUftUboeQEUH9vvcW/8uua/5y/228sYheGjmVmS 9GUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=FKzjo54RIPB2NUwiG8mqiZqKdVRLyqbjaLowygDU56k=; b=NZlINc6BuSiUvIKWaeqy8hU6wXSwElTHpwCP6YBg304lKt77KMV2QpGMUIhk/C23Uh M59i5H/pyJoYpuM12ebc28sBwbSTwmRCYUxRboLi/OrIKmKGiywSIAziMOmV09wSbD7p JTMeHHn3XsdGLFQlhTGjPmSL/Zc5vosyBQMV9zL9r9t6hx3uiFV8R0tN6X+kdE04bs38 NjInHYkrbV2/DqSF7PlXsuNmwlBRLwPaObqwY2IebH00IaHvX6hMT+3xSdconxSU9Rm2 QPUE4X4Dop0BS0PplKGLtYsVBBjocFZ7ftnECR+p3gMUpu7r9g20hVpVySlRi6kq95Cy mtAQ== X-Gm-Message-State: APzg51ABWzIAPRnOUw3EPbdfADjMiLS2VxMGnFbUvlMbe+mJKpkhyRJu chQiHFs2cg1YMVw7eobMpoSzJNcCGHxnN8/ydlBajw== X-Received: by 2002:adf:f5c9:: with SMTP id k9-v6mr7121745wrp.59.1534871079271; Tue, 21 Aug 2018 10:04:39 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:adf:9dcb:0:0:0:0:0 with HTTP; Tue, 21 Aug 2018 10:04:38 -0700 (PDT) In-Reply-To: <20180821074826.GA28079@infradead.org> References: <1534377377-70108-1-git-send-email-atish.patra@wdc.com> <1534377377-70108-4-git-send-email-atish.patra@wdc.com> <20180821074826.GA28079@infradead.org> From: Anup Patel Date: Tue, 21 Aug 2018 22:34:38 +0530 Message-ID: Subject: Re: [RFC PATCH 3/5] RISC-V: Add cpu_operatios structure To: Christoph Hellwig Cc: Atish Patra , Mark Rutland , Damien Le Moal , "palmer@sifive.com" , "linux-kernel@vger.kernel.org List" , "linux-riscv@lists.infradead.org" , Thomas Gleixner Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Aug 21, 2018 at 1:18 PM, Christoph Hellwig wrote: > On Thu, Aug 16, 2018 at 11:51:03AM +0530, Anup Patel wrote: >> Having thought about this more, I think cpu_ops should be an pointer array >> of NR_CPUS size. This means its not necessary to have have same ops for >> all CPUs. The ARM64 implementation of CPU operations also allows separate >> CPU operations for each CPU. >> >> For example, let's us assume that we have an SOC where we 2 cores >> per-cluster and N clusters. All CPUs of cluster0 comes up at the same time >> whereas cluster1 onwards we have to bring-up CPUs using special HW >> mechanism. > > All this (including the patch itself) seems a little hypothetical. > I'd rather only add all this infrastructure once it actually is needed. The cpu_operations is certainly required because SOC vendors will add vendor-specific mechanism to selectively bringing-up CPUs/HARTs instead of all CPUs entering Linux kernel simultaneously. In fact, we might also end-up having CPU ON/OFF operations in SBI. Having separate cpu_operations for each CPU is good for flexibility because CPU clusters might have different way of bringing up CPUs (for example, take any Hetrogeneous Multiprocessor Systems (HMP)). IMHO, RISCV Linux port is new and this the right time to implement critical infrastructure things (such as cpu_operations). Also, its not something radical because we are taking inspiration from existing Linux ports (such as ARM64). Regards, Anup