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[209.132.180.67]) by mx.google.com with ESMTP id w25-v6si14033330pfa.359.2018.08.21.12.34.09; Tue, 21 Aug 2018 12:34:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=JQYVKfTs; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727419AbeHUWa4 (ORCPT + 99 others); Tue, 21 Aug 2018 18:30:56 -0400 Received: from mail.kernel.org ([198.145.29.99]:41150 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727329AbeHUWa4 (ORCPT ); Tue, 21 Aug 2018 18:30:56 -0400 Received: from mail-qt0-f171.google.com (mail-qt0-f171.google.com [209.85.216.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id AB1082183B; Tue, 21 Aug 2018 19:09:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1534878572; bh=TLOTLjFsl2P1EjphIo2lPqxbn1A897ahEznjMY67l2s=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=JQYVKfTsQ0eSgf1jCq5Het9dI7nrMf9VzNWQlx3pk3KNZC1KvvDfQN52mzZdxr8VR A8xMqolliQD6pV5tMvYXzQRSA+d83WUeXsS3NOPuXhZGRiyZrjWZWZqAxvjOkZciGK NI8AWakXQppjwBIaR3wfrcJGdVPxLKz2/COGJ2xc= Received: by mail-qt0-f171.google.com with SMTP id t5-v6so21525822qtn.3; Tue, 21 Aug 2018 12:09:32 -0700 (PDT) X-Gm-Message-State: AOUpUlF5aDXL+c7Dfk86xGhGhUwDeREeg8KrWE1vh4Xhb3RE7VhNW55t k4KVBwszPk7nKG9hhBGZRCkNGYk2SGM9sHPGSA== X-Received: by 2002:aed:2aa1:: with SMTP id t30-v6mr10948764qtd.101.1534878571851; Tue, 21 Aug 2018 12:09:31 -0700 (PDT) MIME-Version: 1.0 References: <1534843809-4137-1-git-send-email-yamada.masahiro@socionext.com> <1534843809-4137-2-git-send-email-yamada.masahiro@socionext.com> In-Reply-To: From: Rob Herring Date: Tue, 21 Aug 2018 14:09:20 -0500 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 1/2] dt-bindings: dmaengine: add DT binding for UniPhier MIO DMAC To: Masahiro Yamada Cc: Vinod , "open list:DMA GENERIC OFFLOAD ENGINE SUBSYSTEM" , Masami Hiramatsu , Jassi Brar , devicetree@vger.kernel.org, "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Aug 21, 2018 at 4:48 AM Masahiro Yamada wrote: > > (+CC Rob, DT, LKML) > > I forgot to CC this to DT community... You really need to resend so that patchwork will pick it up and I'll see it for sure. > > > 2018-08-21 18:30 GMT+09:00 Masahiro Yamada : > > The MIO DMAC (Media IO DMA Controller) is used in UniPhier LD4, > > Pro4, and sLD8 SoCs. > > > > Signed-off-by: Masahiro Yamada > > --- > > > > .../devicetree/bindings/dma/uniphier-mio-dmac.txt | 28 ++++++++++++++++++++++ > > 1 file changed, 28 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/dma/uniphier-mio-dmac.txt > > > > diff --git a/Documentation/devicetree/bindings/dma/uniphier-mio-dmac.txt b/Documentation/devicetree/bindings/dma/uniphier-mio-dmac.txt > > new file mode 100644 > > index 0000000..a9e969e > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/dma/uniphier-mio-dmac.txt > > @@ -0,0 +1,28 @@ > > +UniPhier Media IO DMA controller > > + > > +This works as an external DMA engine for SD/eMMC controllers etc. > > +found in UniPhier LD4, Pro4, sLD8 SoCs. > > + > > +Required properties: > > +- compatible: should be "socionext,uniphier-mio-dmac". > > +- reg: offset and length of the register set for the device. > > +- interrupts: a list of interrupt specifiers associated with the DMA channels. > > +- clocks: a single clock specifier > > +- #dma-cells: should be <1>. The single cell represents the channel number. > > +- dma-channels: specify the number of the DMA channels. This should match to > > + the number of tuples in the interrupts property. > > + > > +Example: > > + dmac: dmac@5a000000 { dma-controller@... > > + compatible = "socionext,uniphier-mio-dmac"; > > + reg = <0x5a000000 0x1000>; > > + interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>, > > + <0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>; > > + clocks = <&mio_clk 7>; > > + #dma-cells = <1>; > > + dma-channels = <8>; > > + }; > > + > > +Note: > > +In the example above, "interrupts = <0 68 4>, <0 68 4>, ..." is not a typo. > > +The first two channels share a single interrupt line. > > -- > > 2.7.4 > > > > > > -- > Best Regards > Masahiro Yamada