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[209.132.180.67]) by mx.google.com with ESMTP id g10-v6si4132112pfd.86.2018.08.23.01.48.47; Thu, 23 Aug 2018 01:49:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=NXy8RTsG; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732742AbeHWMPf (ORCPT + 99 others); Thu, 23 Aug 2018 08:15:35 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:40865 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727122AbeHWMPf (ORCPT ); Thu, 23 Aug 2018 08:15:35 -0400 Received: by mail-pg1-f194.google.com with SMTP id z25-v6so2238712pgu.7 for ; Thu, 23 Aug 2018 01:46:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8GXxtPdBNmvqGpTBgHHAglhjJ/igVIOM0Ya9cZjoLnw=; b=NXy8RTsGvlTCM11EZ4R2JPSVjSwVnrFxBsCXyXfA1kL1NbfEgzb8oXW83EMtZFkUZr +MmHe6/FbUCdIZ22dZGYMB6hTBrVc6SzXTy1a8xWWkwGEJaUh/qrxqWmGB5xX2Uq389f 5xiuL0DaidsHmfU9z1GMA6NXyA5Jj+82fq2OYtlV2pKmWnTv99chWf0XiOtWwm9QX/IP has10nfLX+Mjv/OKmaYCN/stVHVZzC2+V4zxGYCDVTk+0fmXe8qHdIvATBDrwrwOFhVG sqDZ6CvER/BnsSyHtXy8AuikXY/ViWPc8ebjIIPu+9ZZJvAI6/9RGxEQi3dpRRXUVpMu hbKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8GXxtPdBNmvqGpTBgHHAglhjJ/igVIOM0Ya9cZjoLnw=; b=Mq3aKapTgz95tYipxaXA7tU6L1m1GADNMtOmfulG0crbejHr3CM9KgmaXCBSmGlbq1 Qaqy30Osq9NyJzlw5LqmgHOUPAAEgyHH1AGX1wgjEugxb6ncOLtE4lBC3C/I5tv1GSyJ 3pfN864ikWBFUXRRdjKKBeiJLOCKKSsotrj/nTpsHk+7/LULad6eDpZCcww2vvKcwunt OqR8uk2ElREFNfJo0YAu4WONYwZv5eaFhGR9SjEAHdF7xgLjxXz5qjBh+yNdfauQJH+T bueQ0ne2d9y2yY5N9eAVoaS6fNs6sKXbNMytXQj5E01wZDSF7uQpfe7pF8j4G0tPG19R gW6g== X-Gm-Message-State: AOUpUlGecyXBJwdHk+M8rT2tm8Sy2gUe2lKs5rnvDJOz5/SRSd42QoED 25CIg7yLyHNqmHPjLffebVU= X-Received: by 2002:a63:be4a:: with SMTP id g10-v6mr52140410pgo.378.1535014017442; Thu, 23 Aug 2018 01:46:57 -0700 (PDT) Received: from roar.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id x10-v6sm5197706pge.23.2018.08.23.01.46.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 23 Aug 2018 01:46:56 -0700 (PDT) Date: Thu, 23 Aug 2018 18:46:48 +1000 From: Nicholas Piggin To: Peter Zijlstra Cc: torvalds@linux-foundation.org, luto@kernel.org, x86@kernel.org, bp@alien8.de, will.deacon@arm.com, riel@surriel.com, jannh@google.com, ascannell@google.com, dave.hansen@intel.com, linux-kernel@vger.kernel.org, linux-mm@kvack.org, David Miller , Martin Schwidefsky , Michael Ellerman Subject: Re: [PATCH 3/4] mm/tlb, x86/mm: Support invalidating TLB caches for RCU_TABLE_FREE Message-ID: <20180823184648.0439a473@roar.ozlabs.ibm.com> In-Reply-To: <20180822154046.823850812@infradead.org> References: <20180822153012.173508681@infradead.org> <20180822154046.823850812@infradead.org> X-Mailer: Claws Mail 3.16.0 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 22 Aug 2018 17:30:15 +0200 Peter Zijlstra wrote: > Jann reported that x86 was missing required TLB invalidates when he > hit the !*batch slow path in tlb_remove_table(). > > This is indeed the case; RCU_TABLE_FREE does not provide TLB (cache) > invalidates, the PowerPC-hash where this code originated and the > Sparc-hash where this was subsequently used did not need that. ARM > which later used this put an explicit TLB invalidate in their > __p*_free_tlb() functions, and PowerPC-radix followed that example. So this is interesting, I _think_ a145abf12c did fix this bug for powerpc, but then it seem to have been re-broken by a46cc7a90f because that one defers the flush back to tlb_flush time. There was quite a lot of churn getting the radix MMU off the ground at that point though so I'm not 100% sure. But AFAIKS powerpc today has this same breakage, and this patch should fix it. I have a couple of patches that touch the same code I'll send, you might have some opinions on them. Thanks, Nick