Received: by 2002:ac0:a5a6:0:0:0:0:0 with SMTP id m35-v6csp5741028imm; Mon, 27 Aug 2018 03:30:58 -0700 (PDT) X-Google-Smtp-Source: ANB0VdaPTSMd8Fl43mtJbSd7Zzz6ciqtrtIyakrz3TbjGImeFAqXhHwSSqpfC5QxkTFvu0/ol65J X-Received: by 2002:a17:902:aa8f:: with SMTP id d15-v6mr12641167plr.64.1535365858586; Mon, 27 Aug 2018 03:30:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1535365858; cv=none; d=google.com; s=arc-20160816; b=O0SkMqUzWrxZkshMNRS17Itvw0++6J0VTyrEar7dz66sfcO+zSMcp646ENQ4Ufw4Z8 AwwWzsCA4ZobSC/KARNWMpq8U90ZXXuhTvCPBnR26PB+iBHzg/ezs/G1Bc/z19yKxfiS MqMEN9mHCGninZ30VWVEjN1pMySGkxPVQldwzIcTH/RRvdTyl3c1oSvQPNYG3eWoybVn oONhKwgtOnUyoMArTpg2kDB2aEm4/YPwDdHV8OFuDyYTCdhu4wL09JEOd+y0h2WBJxwc pTM2ungNrtRogbgFstkOBs5TynYzRtWkaKIsYPmS7MHGkJ1iLcInA+fqeHwZcPcI7KwQ UIoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding :content-language:in-reply-to:mime-version:user-agent:date :message-id:organization:from:references:cc:to:subject :arc-authentication-results; bh=E4WCWRT1dFJ1pZ6jLg4XwWD6lYf79MMghFmc8RrHsmQ=; b=wawRQo0Ud/ZmM8aV8b/1IEjw2OerYDnKkr98MOg/qqmSmPe++RF/qDGQ/4G42QC3X9 PDTzFJXtq5Dgl5YohWH/UeW3qGN+XOfM8TbA71/eU0JvXWLhYonuW8DTbL8dbyq6qOyJ 2e39pcAjdbO6s+HxRomOs0Vvc2b/vKPveIzR626OR/SGtpL5RQno8nOVahFSuY4/E6uH x0nFbdGFJB8eHobLEbTRAQVx6sTdH0sopJvt9UFW+LlOSalzlxBMOvrEHy0MraGMZ8Vr B7CaaiAoBSYBufR9Z4al7ndVREAf26m0W41qrTuSGh5iNlUol9WhEmenl/IPgSRZn2Ed 9uvg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id bf7-v6si658592plb.76.2018.08.27.03.30.43; Mon, 27 Aug 2018 03:30:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727291AbeH0OO1 (ORCPT + 99 others); Mon, 27 Aug 2018 10:14:27 -0400 Received: from mga02.intel.com ([134.134.136.20]:43340 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726809AbeH0OO1 (ORCPT ); Mon, 27 Aug 2018 10:14:27 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Aug 2018 03:28:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,294,1531810800"; d="scan'208";a="86675663" Received: from ahunter-desktop.fi.intel.com (HELO [10.237.72.137]) ([10.237.72.137]) by orsmga002.jf.intel.com with ESMTP; 27 Aug 2018 03:28:18 -0700 Subject: Re: [PATCH v2 00/40] Tegra SDHCI add support for HS200 and UHS signaling To: Thierry Reding Cc: Aapo Vienamo , Rob Herring , Mark Rutland , Jonathan Hunter , Ulf Hansson , Mikko Perttunen , Stefan Agner , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org References: <1533924522-1037-1-git-send-email-avienamo@nvidia.com> <20180827101036.GB18542@ulmo> From: Adrian Hunter Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Message-ID: Date: Mon, 27 Aug 2018 13:26:35 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <20180827101036.GB18542@ulmo> Content-Type: text/plain; charset=windows-1252 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 27/08/18 13:10, Thierry Reding wrote: > On Fri, Aug 10, 2018 at 09:08:02PM +0300, Aapo Vienamo wrote: >> Hi all, >> >> This series implements support for faster signaling modes on Tegra >> SDHCI controllers. This series consist of several parts: changes >> requried for 1.8 V signaling and pad control, pad calibration, and >> tuning. Following earlies patch sets have been merged into this >> larger set: "Tegra PMC pinctrl pad configuration", "Tegra SDHCI enable >> 1.8 V signaling on Tegar210 and Tegra186", "Tegra SDHCI update the >> padautocal procedure". Also the patches for enabling SDHCI tuning >> are added. >> >> Changelog: >> v2: >> - Fix grammar in PMC device tree bindings docs >> - Remove a stray line from tegra sdhci bindings >> - Cosmetic changes to PMC pinctrl driver >> - Fix a typo in "soc/tegra: pmc: Implement >> tegra_io_pad_is_powered()" commit message >> - Declare mask and value on the same line in >> tegra_io_pad_is_powered() >> - Move the call to tegra_sdhci_is_pad_and_regulator_valid() to >> inside the if condition in tegra_sdhci_reset() >> - Use usleep_range() in tegra_sdhci_configure_cal_pad() >> - Move sdhci_writel() out of the enable if-else body in >> tegra_sdhci_configure_cal_pad() >> - Add a delay before starting polling in >> tegra_sdhci_pad_autocalib() >> - Use usleep_range() in tegra_sdhci_set_tap() >> - Rename orig_enabled to status in >> tegra_sdhci_configure_card_clk() >> - Fix if condition wrapping alignment in tegra_sdhci_set_tap() >> >> v1: >> - Probe the regulator voltage capabilities to determine whether pinctrl >> is needed in tegra_sdhci_r eset >> - Don't remove tegra_sdhci_voltage_switch() >> - Use dev_warn() in tegra_sdhci_init_pinctrl_info() >> - Don't change start_signal_voltage_switch callback if pinctrl info >> invalid >> - Only call udelay(1) on enable in tegra_sdhci_configure_cal_pad() >> - Add nvidia, prefix to pad autocal offset dt props in the example >> >> See the original patch sets for earlier changelogs. >> >> Aapo Vienamo (40): >> dt-bindings: Add Tegra PMC pad configuration bindings >> dt-bindings: mmc: tegra: Add pad voltage control properties >> dt-bindings: Add Tegra SDHCI pad pdpu offset bindings >> dt-bindings: mmc: Add Tegra SDHCI sampling trimmer values >> soc/tegra: pmc: Fix pad voltage configuration for Tegra186 >> soc/tegra: pmc: Factor out DPD register bit calculation >> soc/tegra: pmc: Implement tegra_io_pad_is_powered() >> soc/tegra: pmc: Use X macro to generate IO pad tables >> soc/tegra: pmc: Remove public pad voltage APIs >> soc/tegra: pmc: Implement pad configuration via pinctrl >> mmc: sdhci: Add a quirk to skip clearing the transfer mode register on >> tuning >> mmc: tegra: Reconfigure pad voltages during voltage switching >> mmc: tegra: Poll for calibration completion >> mmc: tegra: Set calibration pad voltage reference >> mmc: tegra: Power on the calibration pad >> mmc: tegra: Disable card clock during pad calibration >> mmc: tegra: Program pad autocal offsets from dt >> mmc: tegra: Perform pad calibration after voltage switch >> mmc: tegra: Enable pad calibration on Tegra210 and Tegra186 >> mmc: tegra: Add a workaround for tap value change glitch >> mmc: tegra: Parse default trim and tap from dt >> mmc: tegra: Configure default tap values >> mmc: tegra: Configure default trim value on reset >> mmc: tegra: Use standard SDHCI tuning on Tegra210 and Tegra186 >> mmc: sdhci: Add a quirk to disable card clock during tuning >> mmc: tegra: Enable workaround for tuning transfer mode bug >> mmc: tegra: Set SDHCI_QUIRK2_TUNE_DIS_CARD_CLK on Tegra210 >> mmc: tegra: Enable UHS and HS200 modes for Tegra210 >> mmc: tegra: Enable UHS and HS200 modes for Tegra186 >> arm64: dts: Add Tegra210 sdmmc pinctrl voltage states >> arm64: dts: Add Tegra186 sdmmc pinctrl voltage states >> arm64: dts: tegra210-p2180: Allow ldo2 to go down to 1.8 V >> arm64: dts: tegra210-p2180: Correct sdmmc4 vqmmc-supply >> arm64: dts: tegra210-p2597: Remove no-1-8-v from sdmmc1 >> arm64: dts: tegra186: Add sdmmc pad auto calibration offsets >> arm64: dts: tegra210: Add sdmmc pad auto calibration offsets >> arm64: dts: tegra210: Add SDHCI tap and trim values >> arm64: dts: tegra186: Add SDHCI tap and trim values >> arm64: dts: tegra186: Assign clocks for sdmmc1 and sdmmc4 >> arm64: dts: tegra210: Assign clocks for sdmmc1 and sdmmc4 >> >> .../bindings/arm/tegra/nvidia,tegra186-pmc.txt | 93 ++++ >> .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 103 ++++ >> .../bindings/mmc/nvidia,tegra20-sdhci.txt | 68 +++ >> arch/arm64/boot/dts/nvidia/tegra186.dtsi | 74 +++ >> arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 12 +- >> arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 1 - >> arch/arm64/boot/dts/nvidia/tegra210.dtsi | 55 ++ >> drivers/mmc/host/sdhci-tegra.c | 556 +++++++++++++++++++-- >> drivers/mmc/host/sdhci.c | 21 + >> drivers/mmc/host/sdhci.h | 4 + >> drivers/soc/tegra/pmc.c | 511 ++++++++++++++----- >> include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h | 18 + >> include/soc/tegra/pmc.h | 20 +- >> 13 files changed, 1324 insertions(+), 212 deletions(-) >> create mode 100644 include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h > > Adrian, > > these patches are also a prerequisite for the UHS signalling changes in > the other two series that Aapo posted. It'd be great if you could take a > quick look and weigh in. Sure, I'll try and have a look today.