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[209.132.180.67]) by mx.google.com with ESMTP id 1-v6si14706151pls.385.2018.08.27.07.36.03; Mon, 27 Aug 2018 07:36:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727612AbeH0SUf (ORCPT + 99 others); Mon, 27 Aug 2018 14:20:35 -0400 Received: from mx2.suse.de ([195.135.220.15]:49994 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727086AbeH0SUe (ORCPT ); Mon, 27 Aug 2018 14:20:34 -0400 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id D655BAFE6; Mon, 27 Aug 2018 14:33:40 +0000 (UTC) From: Mian Yousaf Kaukab To: will.deacon@arm.com, marc.zyngier@arm.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, robert.richter@cavium.com, cwu@amperecomputing.com, Mian Yousaf Kaukab Subject: [PATCH RESEND 1/6] arm64: kpti: move check for non-vulnerable CPUs to a function Date: Mon, 27 Aug 2018 16:33:05 +0200 Message-Id: <20180827143310.641-2-ykaukab@suse.de> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180827143310.641-1-ykaukab@suse.de> References: <20180827143310.641-1-ykaukab@suse.de> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Prepare to call it in generic cpu vulnerabilities support. Signed-off-by: Mian Yousaf Kaukab --- arch/arm64/include/asm/cpufeature.h | 16 ++++++++++++++++ arch/arm64/kernel/cpufeature.c | 9 +-------- 2 files changed, 17 insertions(+), 8 deletions(-) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 1717ba1db35d..0b0b5b3e36ba 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -530,6 +530,22 @@ void arm64_set_ssbd_mitigation(bool state); static inline void arm64_set_ssbd_mitigation(bool state) {} #endif +static inline bool is_cpu_meltdown_safe(void) +{ + /* List of CPUs that are not vulnerable and don't need KPTI */ + static const struct midr_range kpti_safe_list[] = { + MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), + MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), + { /* sentinel */ } + }; + + /* Don't force KPTI for CPUs that are not vulnerable */ + if (is_midr_in_range_list(read_cpuid_id(), kpti_safe_list)) + return true; + + return false; +} + #endif /* __ASSEMBLY__ */ #endif diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index e238b7932096..6a94f8bce35a 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -865,12 +865,6 @@ static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, int scope) { - /* List of CPUs that are not vulnerable and don't need KPTI */ - static const struct midr_range kpti_safe_list[] = { - MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), - MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), - { /* sentinel */ } - }; char const *str = "command line option"; /* @@ -894,8 +888,7 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) return true; - /* Don't force KPTI for CPUs that are not vulnerable */ - if (is_midr_in_range_list(read_cpuid_id(), kpti_safe_list)) + if (is_cpu_meltdown_safe()) return false; /* Defer to CPU feature registers */ -- 2.11.0