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From:   Atish Patra <atish.patra@wdc.com>
To:     palmer@sifive.com, linux-riscv@lists.infradead.org,
        mark.rutland@arm.com, anup@brainfault.org, hch@infradead.org
Cc:     atish.patra@wdc.com, tglx@linutronix.de,
        linux-kernel@vger.kernel.org, damein@vger.kernel.org
Subject: [PATCH v2 0/3] RISC-V: Add new smp features
Date:   Tue, 28 Aug 2018 01:36:07 -0700
Message-Id: <1535445370-19004-1-git-send-email-atish.patra@wdc.com>
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

This patch series implements following smp related features.
Some of the work has been inspired from ARM64.

1. Decouple linux logical cpu ids from hardware cpu id
2. Support cpu hotplug.

Tested on QEMU & HighFive Unleashed board with/without SMP enabled.

v1->v2:

1. Dropped cpu_ops patch.
2. Moved back IRQ cause definiations to irq.h
3. Keep boot cpu hart id and assign zero as the cpu id for boot cpu.
4. Renamed cpu id and hart id correctly. 

Atish Patra (3):
  RISC-V: Add logical CPU indexing for RISC-V
  RISC-V: Use Linux logical cpu number instead of hartid
  RISC-V: Support cpu hotplug.

 arch/riscv/Kconfig                | 12 +++++-
 arch/riscv/include/asm/irq.h      |  1 +
 arch/riscv/include/asm/smp.h      | 33 ++++++++++++++-
 arch/riscv/include/asm/tlbflush.h | 17 ++++++--
 arch/riscv/kernel/cpu.c           |  8 ++--
 arch/riscv/kernel/head.S          | 17 +++++++-
 arch/riscv/kernel/irq.c           | 27 +++++++++++-
 arch/riscv/kernel/process.c       |  7 ++++
 arch/riscv/kernel/setup.c         | 25 ++++++++++-
 arch/riscv/kernel/smp.c           | 51 +++++++++++++++++++----
 arch/riscv/kernel/smpboot.c       | 87 +++++++++++++++++++++++++++++++++------
 arch/riscv/kernel/traps.c         |  6 +--
 drivers/clocksource/riscv_timer.c | 12 ++++--
 drivers/irqchip/irq-sifive-plic.c | 11 +++--
 14 files changed, 269 insertions(+), 45 deletions(-)

-- 
2.7.4