Received: by 2002:ac0:a5a6:0:0:0:0:0 with SMTP id m35-v6csp6929413imm; Tue, 28 Aug 2018 03:38:31 -0700 (PDT) X-Google-Smtp-Source: ANB0VdZQ/e9JNQhmivpxYxCRP2DHNjmkieYCLTn+fWdsMGHtTHJAFGjScrdCx/7lj1jfAdFchAsU X-Received: by 2002:a62:8d7:: with SMTP id 84-v6mr954838pfi.172.1535452711189; Tue, 28 Aug 2018 03:38:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1535452711; cv=none; d=google.com; s=arc-20160816; b=bxO6PDyxuRtgl3MDG/9LSXtU06b4jEImNELR7JS/RlswTzGusVxAv7IZCn9fBAuWBl 1piwb6p+P+A4Lq6LVrstpafhZWYb9GF0HmimxdUy67S1U6zhQ2LWdUfj5DGEpWptm2i4 tyPhP038Dv/3ijKcsA0qu4yH2fTcRXuUu5lasCWF1f1lUSTHSl9SaY3DQWwqUWkV2e6f qblB+4CEAxBe0bGxWDKaJBUAfmhF+iQBGx+z9OYPFoU8Ph2FefYtGKLEQEXVHvIUdq0b Dno6aFyodBg7+scokhI1reZ+IRXh00c5C85eMjFh9jmu86A77Yoq6yInW4Yewc5o7DnI IJmQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:user-agent:references :message-id:in-reply-to:subject:cc:to:from:date :arc-authentication-results; bh=g1JCLzadU/CWHjtAtQmwbG36vJTyIBECbaOgPfO2VxA=; b=fyuq7thqrIe6vRC06/8YgA1ozHrxkv5iQcOU5eWdjVkc6+exYTzb77xMjm3exN5e8q Ksr8wx97zVZXvXXhIzaJXSIakh3wRJ44vMLkSNnLTlKhsf5XeRLuwEib5FhnD0dauZVW XDQR3CFxTG/wpLn0hbh3h7dujrN1KMxBShNP8cQW4NraQ/yKugAVPO48VzTc6FFHgwiz CRXXsocotFvOd4PxGhxqktEAYXNec2Ia89I0qwMoRWnTQ8U/+HS8WgriZ8syRIIjk5wB qE6nRDgyjFXzpUi6lgQJ45j/0EsvBpRf81Yxnje61TqkB9p9J1RDjEi+f8QDfblscqTu ZYzA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g2-v6si655822plp.233.2018.08.28.03.38.15; Tue, 28 Aug 2018 03:38:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727431AbeH1O2I (ORCPT + 99 others); Tue, 28 Aug 2018 10:28:08 -0400 Received: from Galois.linutronix.de ([146.0.238.70]:44328 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727067AbeH1O2I (ORCPT ); Tue, 28 Aug 2018 10:28:08 -0400 Received: from hsi-kbw-5-158-153-52.hsi19.kabel-badenwuerttemberg.de ([5.158.153.52] helo=nanos.tec.linutronix.de) by Galois.linutronix.de with esmtpsa (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1fubMt-0008AZ-5B; Tue, 28 Aug 2018 12:37:03 +0200 Date: Tue, 28 Aug 2018 12:37:02 +0200 (CEST) From: Thomas Gleixner To: Thomas Voegtle cc: x86@kernel.org, LKML , Ingo Molnar , Peter Zijlstra , Dave Hansen Subject: Re: Apollo Lake with newer microcode: not affected by meltdown anymore? In-Reply-To: Message-ID: References: User-Agent: Alpine 2.21 (DEB 202 2017-01-01) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 28 Aug 2018, Thomas Voegtle wrote: > Kernel 4.18.5 with old microcode: > > [ 0.000000] microcode: microcode updated early to revision 0x2c, date = > 2017-03-25 > cat /sys/devices/system/cpu/vulnerabilities/meltdown > Mitigation: PTI > > > Kernel 4.18.5 with new microcode (microcode-20180807.tgz), same config: > > [ 0.000000] microcode: microcode updated early to revision 0x32, date = > 2018-05-11 > cat /sys/devices/system/cpu/vulnerabilities/meltdown > Not affected > > > This happens with 4.14.y and 4.9.y as well. > > The same with ssb: > old microcode: spec_store_bypass:Vulnerable > new microcode: spec_store_bypass:Not affected > > Is this intentional behavior? I have never seen this on other CPUs, such > as Gemini Lake or Baytrail, Haswell etc. Looks like the micro code update has the relevant bits set in the IA32_ARCH_CAPABILITIES MSR, which tell the kernel that the CPU is not vulnerable. So it seems Intel was able to mitigate the mess in micro code for this particular CPU model. Thanks, tglx