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From:   Arnd Bergmann <arnd@arndb.de>
Date:   Tue, 28 Aug 2018 14:57:05 +0200
Message-ID: <CAK8P3a0+zJRxEYWZpYShRJo-3oqMaC9TJADugaRTiBnjw7ssPA@mail.gmail.com>
Subject: Re: [PATCH 10/15] soc: octeontx2: Reconfig MSIX base with IOVA
To:     Sunil Kovvuri <sunil.kovvuri@gmail.com>
Cc:     Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Olof Johansson <olof@lixom.net>,
        Linux ARM <linux-arm-kernel@lists.infradead.org>,
        linux-soc@vger.kernel.org, gakula@marvell.com,
        sgoutham@marvell.com, Thomas Gleixner <tglx@linutronix.de>,
        Marc Zyngier <marc.zyngier@arm.com>,
        Jason Cooper <jason@lakedaemon.net>,
        linux-pci <linux-pci@vger.kernel.org>
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On Tue, Aug 28, 2018 at 2:42 PM Sunil Kovvuri <sunil.kovvuri@gmail.com> wrote:
>
> On Tue, Aug 28, 2018 at 5:39 PM Arnd Bergmann <arnd@arndb.de> wrote:
> >
> > On Tue, Aug 28, 2018 at 12:58 PM <sunil.kovvuri@gmail.com> wrote:
> > >
> > > From: Geetha sowjanya <gakula@marvell.com>
> > >
> > > HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence
> > > create a IOMMU mapping for the physcial address configured by
> > > firmware and reconfig RVU_AF_MSIXTR_BASE with IOVA.
> > >
> > > Signed-off-by: Geetha sowjanya <gakula@marvell.com>
> > > Signed-off-by: Sunil Goutham <sgoutham@marvell.com>
> >
> > I think this needs some more explanation. What is the difference between
> > the MSI-X support in this driver and every other one? Are you working
> > around a hardware bug, or is there something odd in the implementation
> > of your irqchip driver? Do you use a GIC to handle the MSI interrupts
> > or something else?
>
> This admin function is a PCI device which is capable of provisioning
> HW blocks to other PCIe SRIOV devices in the system. Each HW block
> (eg memory buffer pools, NIC dewscriptors, crypto engines e.t.c) needs
> certain no of MSIX vectors. Admin function has a set of 32K MSIX vectors
> in memory (not on-chip) which based on HW block provisioning to a PCI device
> attaches the required number of vectors to that device. Some part of this
> configuration is done by low level firmware.
>
> RVU_AF_MSIXTR_BASE points to the memory region allocated for 32K MSIX
> vectors. If kernel is booted with IOMMU enabled and admin function device
> is attached to SMMU, HW will go through translation to access this MSIX
> vector memory region. Hence the mapping done in this patch.

Do you mean this is not a regular PCIe MSI-X interrupt to the GIC, but
something internal to your device that gets routed through the IOMMU
back into the device?

I'm still confused.

       Arnd