Received: by 2002:ac0:a5a6:0:0:0:0:0 with SMTP id m35-v6csp7247768imm;
        Tue, 28 Aug 2018 08:43:04 -0700 (PDT)
X-Google-Smtp-Source: ANB0VdYdkYhnP/Ds3gCHv/UWtWDgE5ynfqwXNm/bO0+ObvS5T1bsHXZA2no5Q1H+G5wXg9uBVeVD
X-Received: by 2002:a63:990a:: with SMTP id d10-v6mr2122182pge.80.1535470984236;
        Tue, 28 Aug 2018 08:43:04 -0700 (PDT)
ARC-Seal: i=1; a=rsa-sha256; t=1535470984; cv=none;
        d=google.com; s=arc-20160816;
        b=y+WWviQ8WHi/JMF5hzzxk5RdlryCT9/9UAA0VNcFJ39ugs/L7vr6TLaLVTdqNsY7xM
         Apu58OWVNfpS4kJDaoPOn9O2M81nIFdU7ybDBl5kbeINuIUMCrHuVjEi9P3YpPRlOlJE
         1jG81g3i1C9SYjqqn9MCJTTSXN5rlacj5/S41xzf/GvViBJdsyG84YwrbdUINwp8oED4
         Wg7Her1fyIK34QvrUmYhASnQt2DQj/CwTrnwlFy5nV+W0U5SpgXkRo7Aq39QZElQapKD
         VZmnOAxmN282yxoT5vYuVKMJ9auwlJj0FTbJjTFzIemHUGOknNhhnNF2DhQYVhaw74AC
         h1jg==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816;
        h=list-id:precedence:sender:content-transfer-encoding:mime-version
         :references:in-reply-to:message-id:subject:cc:to:from:date
         :arc-authentication-results;
        bh=CVnOA/Ld+a3J4F9fDpwxhajPyEKyJIzIvmWzjE8Cock=;
        b=vu9aSukWRQ6nqBoyF7DgPURnY4OcKxc7PEPqJbqLAlGwpdHMnINamu/VK+VyLZz143
         zHhzlm9GvtaP+6b86iUs26LR4u2Dl8srpoIWRdCzXZJottnJKlpkjw+OBlKI4ULgJDb/
         oSb3f/wCRLnQiTuR5wVtp1mdOcDUGBA2h+Eh4Jaws9pbeHn89nRq4rBqgabG+5NtzRPL
         DP6LExcOj1tWCcdIqK9N7xmtMFuVmd8d8JhP9XTIp6+H5TgZTY/fqeyfFy058chvWaIp
         QzGBRXE2mvsK/l7s6VKxYtCSRpiZvkOGwaVySa2tZ4vL7ORGjPDhWvUwv3GmWfmew3OA
         QDqg==
ARC-Authentication-Results: i=1; mx.google.com;
       spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org;
       dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com
Return-Path: <linux-kernel-owner@vger.kernel.org>
Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67])
        by mx.google.com with ESMTP id d24-v6si1304876pgb.226.2018.08.28.08.42.47;
        Tue, 28 Aug 2018 08:43:04 -0700 (PDT)
Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
Authentication-Results: mx.google.com;
       spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org;
       dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
        id S1727166AbeH1Tdw (ORCPT <rfc822;radocaj.bane@gmail.com>
        + 99 others); Tue, 28 Aug 2018 15:33:52 -0400
Received: from hqemgate16.nvidia.com ([216.228.121.65]:4206 "EHLO
        hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org
        with ESMTP id S1726383AbeH1Tdw (ORCPT
        <rfc822;linux-kernel@vger.kernel.org>);
        Tue, 28 Aug 2018 15:33:52 -0400
Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA)
        id <B5b856d280000>; Tue, 28 Aug 2018 08:41:28 -0700
Received: from HQMAIL101.nvidia.com ([172.20.161.6])
  by hqpgpgate101.nvidia.com (PGP Universal service);
  Tue, 28 Aug 2018 08:41:38 -0700
X-PGP-Universal: processed;
        by hqpgpgate101.nvidia.com on Tue, 28 Aug 2018 08:41:38 -0700
Received: from dhcp-10-21-25-168 (10.21.25.201) by HQMAIL101.nvidia.com
 (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 28 Aug
 2018 15:41:35 +0000
Date:   Tue, 28 Aug 2018 18:41:29 +0300
From:   Aapo Vienamo <avienamo@nvidia.com>
To:     Adrian Hunter <adrian.hunter@intel.com>
CC:     Rob Herring <robh+dt@kernel.org>,
        Mark Rutland <mark.rutland@arm.com>,
        Thierry Reding <thierry.reding@gmail.com>,
        Jonathan Hunter <jonathanh@nvidia.com>,
        Ulf Hansson <ulf.hansson@linaro.org>,
        "Mikko Perttunen" <mperttunen@nvidia.com>,
        Stefan Agner <stefan@agner.ch>, <devicetree@vger.kernel.org>,
        <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <linux-mmc@vger.kernel.org>
Subject: Re: [PATCH v2 25/40] mmc: sdhci: Add a quirk to disable card clock
 during tuning
Message-ID: <20180828184129.525439ba@dhcp-10-21-25-168>
In-Reply-To: <b0b761ac-00fb-5a79-7a38-89b08c620c02@intel.com>
References: <1533924522-1037-1-git-send-email-avienamo@nvidia.com>
        <1533924522-1037-26-git-send-email-avienamo@nvidia.com>
        <b0b761ac-00fb-5a79-7a38-89b08c620c02@intel.com>
X-NVConfidentiality: public
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
X-Originating-IP: [10.21.25.201]
X-ClientProxiedBy: UKMAIL102.nvidia.com (10.26.138.15) To HQMAIL101.nvidia.com
 (172.20.187.10)
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

On Mon, 27 Aug 2018 14:25:44 +0300
Adrian Hunter <adrian.hunter@intel.com> wrote:

> On 10/08/18 21:08, Aapo Vienamo wrote:
> > Add a quirk to disable card clock when the tuning command is sent.
> > 
> > This has to be done to prevent the SDHCI controller from hanging on
> > Tegra210. Without the quirk enabled there appears to be around 10%
> > chance that the tuning sequence will fail and time out due to the
> > controller locking up.
> > 
> > Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
> > ---
> >  drivers/mmc/host/sdhci.c | 15 +++++++++++++++
> >  drivers/mmc/host/sdhci.h |  2 ++
> >  2 files changed, 17 insertions(+)
> > 
> > diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> > index 04dc443..166b16f 100644
> > --- a/drivers/mmc/host/sdhci.c
> > +++ b/drivers/mmc/host/sdhci.c
> > @@ -2175,6 +2175,7 @@ static void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
> >  	struct mmc_request mrq = {};
> >  	unsigned long flags;
> >  	u32 b = host->sdma_boundary;
> > +	u16 clk;
> >  
> >  	spin_lock_irqsave(&host->lock, flags);
> >  
> > @@ -2183,6 +2184,13 @@ static void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
> >  	cmd.mrq = &mrq;
> >  
> >  	mrq.cmd = &cmd;
> > +
> > +	if (host->quirks2 & SDHCI_QUIRK2_TUNE_DIS_CARD_CLK) {
> > +		clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
> > +		clk &= ~SDHCI_CLOCK_CARD_EN;
> > +		sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);  
> 
> Rather than using a quirk, could you use the sdhci I/O accessors to disable
> the clock before the tuning comment is written, udelay(1), and then enable
> it again?

This was the way it was implemented in the downstream kernel. However,
doing it in the IO accessor when a tuning command is sent seems to work
too.

 -Aapo