Received: by 2002:ac0:a5a6:0:0:0:0:0 with SMTP id m35-v6csp7257216imm; Tue, 28 Aug 2018 08:53:21 -0700 (PDT) X-Google-Smtp-Source: ANB0Vdb5mCNAxqIss3EziWM8lKC2UdEo+vfaQz2irIJC3oL8mlANI2gpY8hyb7U9HDIOXP74BbDr X-Received: by 2002:a63:2583:: with SMTP id l125-v6mr2139948pgl.70.1535471601274; Tue, 28 Aug 2018 08:53:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1535471601; cv=none; d=google.com; s=arc-20160816; b=CEbO6W8kuwkPnD4uUJ20dy3Kyl2imwM+x0odpaNBvG0T74OHO04RsJaTP2QdNtv+gy LwcyLuULVjBgJ6TJORRUGmgmZR0JYZzFClAFTBDCGbKGrqtxCQjHzdNqNkJNtyH6uhZA x/9Oihid5bqb3thetOySGJNqulfRC6XMkDhH0214NAbLhQITLBvM9s/OdyE3j2KjH0WL fTCg63wdiKOhDcRd+8LRCC3HD1aIbtDejoXThUTeMCPSoCAh5NPnsC6vOrZ3Jt1iVs2z nqrscgXTZAmpFN/45Rm0eOggtRPveOUeDa32IYO1fa0m3QxrL3/Uc4u3qMphgRQCP4jv 8Hlg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=cvjIYquDGUPKkJ3hE86F4bWGg3PQyN+Mj29tseUeyzw=; b=EHblwxMzn0gk0k4q/f9jaiqTrocsOWxWvlF93sILul051NLIxsgE+YniWzV4oAFe7i DndxNcqpd09RkQeOaptLeLUkZSOVD65zCEYYo4/2Nt/5V8T1zMhDujqDqLnPUjyjgmQz V+5L9tTchKYeGtmTLvJYg7cxyCRPw+FX9+r1XZDrYaV/4EjgcXNAiwnybM2SzbxLFS0B dQ3CZ6vS4W78TbPxHY64s7iCdUt497xRPYnlao72y8ObvFUJX3OEW2hfBEeg8Lh8dXK0 4YXYdLqYpRF9miYnvF5P05e976ON9gPJSgB3StzceppaVo5GAZ52i1KNXsSQFqlI5D7F A0oA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b34-v6si1315135plc.170.2018.08.28.08.53.05; Tue, 28 Aug 2018 08:53:21 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727271AbeH1ToI (ORCPT + 99 others); Tue, 28 Aug 2018 15:44:08 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:40914 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726383AbeH1ToH (ORCPT ); Tue, 28 Aug 2018 15:44:07 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 03309ED1; Tue, 28 Aug 2018 08:51:51 -0700 (PDT) Received: from e112298-lin.Emea.Arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id DC8F43F557; Tue, 28 Aug 2018 08:51:48 -0700 (PDT) From: Julien Thierry To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, daniel.thompson@linaro.org, joel@joelfernandes.org, marc.zyngier@arm.com, mark.rutland@arm.com, christoffer.dall@arm.com, james.morse@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, Julien Thierry , Suzuki K Poulose Subject: [PATCH v5 01/27] arm64: cpufeature: Set SYSREG_GIC_CPUIF as a boot system feature Date: Tue, 28 Aug 2018 16:51:11 +0100 Message-Id: <1535471497-38854-2-git-send-email-julien.thierry@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1535471497-38854-1-git-send-email-julien.thierry@arm.com> References: <1535471497-38854-1-git-send-email-julien.thierry@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Signed-off-by: Julien Thierry Suggested-by: Daniel Thompson Cc: Catalin Marinas Cc: Will Deacon Cc: Suzuki K Poulose Cc: Marc Zyngier --- arch/arm64/kernel/cpufeature.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index e238b79..1e433ac 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1039,7 +1039,7 @@ static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused) { .desc = "GIC system register CPU interface", .capability = ARM64_HAS_SYSREG_GIC_CPUIF, - .type = ARM64_CPUCAP_SYSTEM_FEATURE, + .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, .matches = has_useable_gicv3_cpuif, .sys_reg = SYS_ID_AA64PFR0_EL1, .field_pos = ID_AA64PFR0_GIC_SHIFT, -- 1.9.1