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[209.132.180.67]) by mx.google.com with ESMTP id f10-v6si2949189pfn.85.2018.08.29.01.15.57; Wed, 29 Aug 2018 01:16:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=KSz8vis2; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728161AbeH2MKI (ORCPT + 99 others); Wed, 29 Aug 2018 08:10:08 -0400 Received: from mail-wr1-f68.google.com ([209.85.221.68]:44088 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728128AbeH2MKH (ORCPT ); Wed, 29 Aug 2018 08:10:07 -0400 Received: by mail-wr1-f68.google.com with SMTP id v16-v6so3887200wro.11; Wed, 29 Aug 2018 01:14:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:reply-to:from:date:message-id :subject:to:cc; bh=fyWwnWzhTFxdNzOlw/kjrykPJ9vCKYMC9ZTioASyThw=; b=KSz8vis2Fk3l8eIRcL4yRZ9ScD18rWcBkTew67KbiH1TF6iE0s3z2LB6BCBoSv+0jw xQDESQ8+NNIqcatF3PDjX4R7aLaiXn7uFyWwigm/58f+0TIrS96M0T4nSfxim46B7zwN SI7Ta1wbzhuGpO0mv7f6WxSPMa98QByyrEwGH/ivPl6ihMfo1+GoKY4ud3qe4bevFODL Q+a3GAWF9fzFauVsZAWDJlfT18bF215xXzYUEfKBPxVLTG3P0LxUAQJc9CJ7FoJ0myVf BQAREb9A6Y7cUcAknYrtpA6WFYWLQmGOLrJ7slpDE//cwD0hXWz9e27HcUeIRvmld0qb AYaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:reply-to :from:date:message-id:subject:to:cc; bh=fyWwnWzhTFxdNzOlw/kjrykPJ9vCKYMC9ZTioASyThw=; b=J9cDRUSf0yzqAJ+gaxQ0eviK6Un6L5c3lrb8WyYsPELI/iRxn2koozXUiErz+fgcFn DPLzHApTDiTx418gko/C92w/DBkDivuhR+aTAPp5mEo3IvsoOae88UbBBJ+rJ9HxBAxQ a+K4GhP1xHG3z4ARDpHWesTE686l7Rhx42Jf80HqKXZX7NPW62ezSQGIjPLKrpte4Gof KoGEilq9NeFIaUALSQyffJxmndjGzHttppZaNEp/YZSbaqDv7M/Y2V819KmfAgofUNEv 3U0bgFXvQF0v4HFvK0GloBFPqgNkrhOylvlNWAQq0HMwSmYi0PUoydRY2NwQzZ+rItan OX8Q== X-Gm-Message-State: APzg51AIYtfYDtrcxb0pMhOwSCtbsqInSlNgC9jZPKKLJiiWFtMItRaq o/v3mbMeugPW72BVqqkv/WyB4u5KPJb+fmAXlmA= X-Received: by 2002:adf:80ea:: with SMTP id 97-v6mr3387445wrl.57.1535530465001; Wed, 29 Aug 2018 01:14:25 -0700 (PDT) MIME-Version: 1.0 References: <20180802141012.19970-1-andrea.merello@gmail.com> <20180802141012.19970-3-andrea.merello@gmail.com> <20180827053103.GU2388@vkoul-mobl> In-Reply-To: <20180827053103.GU2388@vkoul-mobl> Reply-To: andrea.merello@gmail.com From: Andrea Merello Date: Wed, 29 Aug 2018 10:14:12 +0200 Message-ID: Subject: Re: [PATCH v4 3/7] dt-bindings: dmaengine: xilinx_dma: add optional xlnx,sg-length-width property To: Vinod Cc: dan.j.williams@intel.com, michal.simek@xilinx.com, appana.durga.rao@xilinx.com, dmaengine@vger.kernel.org, linux-kernel , Rob Herring , Mark Rutland , devicetree , Radhey Shyam Pandey Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Aug 27, 2018 at 7:31 AM Vinod wrote: > > On 02-08-18, 16:10, Andrea Merello wrote: > > The width of the "length register" cannot be autodetected, and it is now > > specified with a DT property. Add DOC for it. > > Add Documentation for it... OK > > > > Cc: Rob Herring > > Cc: Mark Rutland > > Cc: devicetree@vger.kernel.org > > Cc: Radhey Shyam Pandey > > Signed-off-by: Andrea Merello > > Reviewed-by: Radhey Shyam Pandey > > --- > > Changes in v2: > > - change property name > > - property is now optional > > - cc DT maintainer > > Changes in v3: > > - reword > > - cc DT maintainerS and ML > > Changes in v4: > > - specify the unit, the valid range and the default value > > --- > > Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt > > index a2b8bfaec43c..aec4a41a03ae 100644 > > --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt > > +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt > > @@ -41,6 +41,10 @@ Optional properties: > > - xlnx,include-sg: Tells configured for Scatter-mode in > > the hardware. > > Optional properties for AXI DMA: > > +- xlnx,sg-length-width: Should be set to the width in bits of the length > > + register as configured in h/w. Takes values {8...26}. If the property > > + is missing or invalid then the default value 23 is used. This is the > > + maximum value that is supported by all IP versions. > > - xlnx,mcdma: Tells whether configured for multi-channel mode in the hardware. > > Optional properties for VDMA: > > - xlnx,flush-fsync: Tells which channel to Flush on Frame sync. > > -- > > 2.17.1 > > -- > ~Vinod