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[209.132.180.67]) by mx.google.com with ESMTP id d39-v6si3649968pla.41.2018.08.29.05.10.57; Wed, 29 Aug 2018 05:11:13 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cvAiSkJZ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727704AbeH2QG2 (ORCPT + 99 others); Wed, 29 Aug 2018 12:06:28 -0400 Received: from mail-it0-f65.google.com ([209.85.214.65]:33785 "EHLO mail-it0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727562AbeH2QG2 (ORCPT ); Wed, 29 Aug 2018 12:06:28 -0400 Received: by mail-it0-f65.google.com with SMTP id j198-v6so4931524ita.0 for ; Wed, 29 Aug 2018 05:09:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=gtU6YyhgXVj7dccZ3H+KpHZdMVIScyinN3wtISC1poA=; b=cvAiSkJZe2pCoues+D6TOR/DIaUkvEFcgQJs/hsbsJuuHGBDQKFK/w74clDcDWd4CI D8pFxcj94OxAW4iG0xYu/CjyX9u4rK+hlwtEaNwDcMKkDro0MFqn+kw7XjztcDXQg5pC 1H3AmTMvjdlrTl0i/qr1WSdISeyp7UborI8iI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=gtU6YyhgXVj7dccZ3H+KpHZdMVIScyinN3wtISC1poA=; b=tzfZbVOxHWWUI/IZp1qPtVIYj3oD5UI4lrwQkK6GklHHhCIwdlkXk7RZIPpuVHe2hb WSNIq554+dOhZzzTklPrCWtPznELrCRzoRZDSFKIYid8f6HASm6BvTxavzVp3cgxdaCi AtoKrJPJAmCGD9hTjFWKuPcgrfedUx45gaEc5YzzT33aqInui2Ix0pSvi0myOLUJY1Ks Pzo3hJC4EUon2B5YpalyEN/8MIHwBcIzEPtMju//ZXwsyNh9hWovzXbMipbTQ/NlstJ1 9ROvgAilYW2kY7ZG3IBlftz6cnwDjzybI03pIZ9C7/NU6WLjoxtXSR6+zLW3K+OLg9m9 Tk/w== X-Gm-Message-State: APzg51B2AEcHz6Mu0nJNbBRPFiHZSk8RjtZ/GpUZvVHnBl2lbnDoZ4E8 3MSy5MYcUJt9rNFFuQ4srpGMd1+UZp3w4/ZEI2U9dw== X-Received: by 2002:a24:144:: with SMTP id 65-v6mr4668022itk.62.1535544591542; Wed, 29 Aug 2018 05:09:51 -0700 (PDT) MIME-Version: 1.0 References: <1533522556-55055-1-git-send-email-aditya@kobol.io> <1533522556-55055-2-git-send-email-aditya@kobol.io> <20180829100229.7566e0db@windsurf> In-Reply-To: <20180829100229.7566e0db@windsurf> From: Linus Walleij Date: Wed, 29 Aug 2018 14:09:37 +0200 Message-ID: Subject: Re: [PATCH RESEND 1/2] gpio: mvebu: Add support for multiple PWM lines per GPIO chip To: Thomas Petazzoni Cc: aditya@kobol.io, "thierry.reding@gmail.com" , Thomas Petazzoni , Jason Cooper , "open list:GPIO SUBSYSTEM" , Richard Genoud , Gregory Clement , gauthier@kobol.io, Alban Browaeys , linux-pwm@vger.kernel.org, "linux-kernel@vger.kernel.org" , Dennis Gilmore , Ralph Sennhauser , Andrew Lunn Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Aug 29, 2018 at 10:02 AM Thomas Petazzoni wrote: > Andrew Lunn did the initial support for PWM in this driver, and he > outlined in the commit log the limitation of his first implementation: > > However, there are only two sets of PWM configuration registers for > all the GPIO lines. This driver simply allows a single GPIO line per > GPIO chip of 32 lines to be used as a PWM. Attempts to use more > return EBUSY. > > Andrew, perhaps you could review the patch posted by Aditya, since you > already looked at PWM support on mvebu platforms ? Thanks yes Andrew is involved, I will wait for Andrew's definitive ACK before merging any of this. Yours, Linus Walleij