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Fri, 31 Aug 2018 08:04:09 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=GUcJrMxTIlguw1xb+2RdgubEaqGvJQvmMyWfRvHMyQI=; b=P9c7gjrL1bEpG6myi+kuo79V1PGN4f04EWhhWM2HNfdMqPeHx4AcvdeixdUGtgA3yNAtjG7tZvFm0/j0By4hlkIQxNEzjRuGSbd57j8dbiWON7gsbWVXrYTUL42qYM/S2/YZXYWDrUAQr39JLRm+lePrfJydyp+R0jZti/7yPo8= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=anson.huang@nxp.com; Received: from anson-OptiPlex-790.ap.freescale.net (119.31.174.66) by AM0PR0402MB3907.eurprd04.prod.outlook.com (2603:10a6:208:f::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1101.17; Fri, 31 Aug 2018 07:57:42 +0000 From: Anson Huang To: shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, fabio.estevam@nxp.com, robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, mturquette@baylibre.com, sboyd@kernel.org, colin.didier@devialet.com, clement.peron@devialet.com, ping.bai@nxp.com, aisheng.dong@nxp.com, shengjiu.wang@nxp.com, matteo.lisi@engicam.com, michael@amarulasolutions.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: Linux-imx@nxp.com Subject: [PATCH 0/7] Add i.MX6 SoCs mmdc ipg clocks management Date: Fri, 31 Aug 2018 15:53:11 +0800 Message-Id: <1535701998-20443-1-git-send-email-Anson.Huang@nxp.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [119.31.174.66] X-ClientProxiedBy: HK0PR01CA0037.apcprd01.prod.exchangelabs.com (2603:1096:203:3e::25) To AM0PR0402MB3907.eurprd04.prod.outlook.com (2603:10a6:208:f::27) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 42cc4920-30c1-4822-a7c6-08d60f1773a7 X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:(7020095)(4652040)(8989137)(4534165)(4627221)(201703031133081)(201702281549075)(8990107)(5600074)(711020)(4618075)(2017052603328)(7153060)(7193020);SRVR:AM0PR0402MB3907; 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To make it more formal, this patch set add all available MMDC IPG clocks into clock tree, and add optional clocks enable operation in MMDC driver to make sure IPG clock is enabled before accessing registers, and passing MMDC IPG clock info from device tree MMDC node. In order to NOT break old device tree, this patch set does NOT remove the CLK_IS_CRITIAL flag for MMDC0 IPG clock. Anson Huang (7): ARM: imx: add mmdc ipg clock operation for mmdc clk: imx6ul: add mmdc1 ipg clock clk: imx6sx: add mmdc1 ipg clock clk: imx6sll: add mmdc1 ipg clock clk: imx6sl: add mmdc ipg clocks clk: imx6q: add mmdc0 ipg clock ARM: dts: imx6: add mmdc ipg clock arch/arm/boot/dts/imx6qdl.dtsi | 1 + arch/arm/boot/dts/imx6sl.dtsi | 1 + arch/arm/boot/dts/imx6sll.dtsi | 1 + arch/arm/boot/dts/imx6sx.dtsi | 1 + arch/arm/boot/dts/imx6ul.dtsi | 1 + arch/arm/mach-imx/mmdc.c | 14 ++++++++++++++ drivers/clk/imx/clk-imx6q.c | 1 + drivers/clk/imx/clk-imx6sl.c | 2 ++ drivers/clk/imx/clk-imx6sll.c | 1 + drivers/clk/imx/clk-imx6sx.c | 1 + drivers/clk/imx/clk-imx6ul.c | 1 + include/dt-bindings/clock/imx6qdl-clock.h | 3 ++- include/dt-bindings/clock/imx6sl-clock.h | 4 +++- include/dt-bindings/clock/imx6sll-clock.h | 3 ++- include/dt-bindings/clock/imx6sx-clock.h | 3 ++- include/dt-bindings/clock/imx6ul-clock.h | 3 ++- 16 files changed, 36 insertions(+), 5 deletions(-) -- 2.7.4