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[209.132.180.67]) by mx.google.com with ESMTP id 1-v6si15853068pln.415.2018.09.03.07.10.23; Mon, 03 Sep 2018 07:10:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727700AbeICS3F (ORCPT + 99 others); Mon, 3 Sep 2018 14:29:05 -0400 Received: from mail.bootlin.com ([62.4.15.54]:37580 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727659AbeICS3F (ORCPT ); Mon, 3 Sep 2018 14:29:05 -0400 Received: by mail.bootlin.com (Postfix, from userid 110) id 2E77D208B5; Mon, 3 Sep 2018 16:08:44 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.bootlin.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost (242.171.71.37.rev.sfr.net [37.71.171.242]) by mail.bootlin.com (Postfix) with ESMTPSA id 0233120618; Mon, 3 Sep 2018 16:08:43 +0200 (CEST) From: Alexandre Belloni To: Shawn Guo Cc: Li Yang , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Alexandre Belloni Subject: [PATCH v2 3/5] arm64: dts: fsl: ls1046a: disable uarts by default Date: Mon, 3 Sep 2018 16:08:38 +0200 Message-Id: <20180903140840.23648-3-alexandre.belloni@bootlin.com> X-Mailer: git-send-email 2.19.0.rc1 In-Reply-To: <20180903140840.23648-1-alexandre.belloni@bootlin.com> References: <20180903140840.23648-1-alexandre.belloni@bootlin.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Disable the UARTs by defaultto avoid registering unused UARTs. This effectively change the number of registered UARTS for the RDB and QDS from 4 to 2 but this seems the right thing to do. It is especially useful when connecting other 8250 uart on PCIe for example as the default maximum number of 8250 UARTs that can be registered is 4. Signed-off-by: Alexandre Belloni --- arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 2d8122019cd8..62ae3ee19d6f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -423,6 +423,7 @@ reg = <0x00 0x21c0500 0x0 0x100>; interrupts = ; clocks = <&clockgen 4 1>; + status = "disabled"; }; duart1: serial@21c0600 { @@ -430,6 +431,7 @@ reg = <0x00 0x21c0600 0x0 0x100>; interrupts = ; clocks = <&clockgen 4 1>; + status = "disabled"; }; duart2: serial@21d0500 { @@ -437,6 +439,7 @@ reg = <0x0 0x21d0500 0x0 0x100>; interrupts = ; clocks = <&clockgen 4 1>; + status = "disabled"; }; duart3: serial@21d0600 { @@ -444,6 +447,7 @@ reg = <0x0 0x21d0600 0x0 0x100>; interrupts = ; clocks = <&clockgen 4 1>; + status = "disabled"; }; gpio0: gpio@2300000 { -- 2.19.0.rc1