Received: by 2002:ac0:a5a6:0:0:0:0:0 with SMTP id m35-v6csp2294957imm; Tue, 4 Sep 2018 01:48:06 -0700 (PDT) X-Google-Smtp-Source: ANB0VdbVuTLRH6CAuGqJDg8372KL5m4eMw/SUAUjK6adnEa1VHgMeg04vHhNTtf1kNEnGb4pqtWg X-Received: by 2002:a17:902:8481:: with SMTP id c1-v6mr32679165plo.177.1536050886618; Tue, 04 Sep 2018 01:48:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1536050886; cv=none; d=google.com; s=arc-20160816; b=Tk1RM+E5oFiJhgQSCriRhT1D0b7eGc3GuvK8JfTWOeiS9dIuspo3ipAqpykR4N7QUn FPVLW6jkETzGgO9qB/+scqACLIep0hZTuxbIlTdqMo4M+3L3j9J8KsLMc7ijY4+5C722 ub9M4wnOseRWTcpw0NkHwYSfBK6IAdIvrb2x6L7+BqaFpD+YtTBgF+h1tJG2d7Dvrt2d 7NFSOKmlGAgu6G1+Z1pd3TsJIPHIivprYy8shZ6WB2wcNfyjDe6L/2LG74TJnJ8dpjUt ZM2W77NsNCksFkX3oUMOzWCXeosPv7wPIC3oL+O9u3ICvroJUrqpoxKfjttpbkPT8r2F 8zGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:arc-authentication-results; bh=N8WWyBJgB/DviywyOo9SN1ASSdBt6oThPa/ZI9Kwk9U=; b=xsRGXSYTObPDDjkWD/N+Z1dA8VOnkqEAknyRHkCdraVg5lJ3tttiu0nGmyanWpHb1B kGWhp3xoaauqUFfxv718frZRk9esA3d1ZxKU/vwpnN+QPRhGfAAVBv2zhYbfYvEGEQZ+ avK07vQH1VmpFNEx9WwIkflJvJoZB0ZXUqHHZAejiR3NIwf04Ys4knEzKBef2ecs9h3C AcQVlPWNXiYZgW5i5a0Zo2u7Y2tqj5NWp2zWrcgPc8HiOZh2U1JjoGt5T/+rHLDskjhA /fFEQ3gQEv/VlS629fvLZrd3TRM/h58fVu8SWI3pkT04/MXzhTv9HUM6oLvWZSsdKeLQ X7Sw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b1-v6si18755343pls.367.2018.09.04.01.47.20; Tue, 04 Sep 2018 01:48:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727289AbeIDNIR (ORCPT + 99 others); Tue, 4 Sep 2018 09:08:17 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:18561 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726167AbeIDNIQ (ORCPT ); Tue, 4 Sep 2018 09:08:16 -0400 X-UUID: f7422fe332bf4b6fbf5f5b9783a7bbb7-20180904 Received: from mtkcas09.mediatek.inc [(172.21.101.178)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1196073376; Tue, 04 Sep 2018 16:44:00 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Tue, 4 Sep 2018 16:43:57 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Tue, 4 Sep 2018 16:43:57 +0800 From: To: Sean Wang , Vinod Koul , Rob Herring , Matthias Brugger , Dan Williams CC: , , , , , Subject: [PATCH] add support for Mediatek Command-Queue DMA controller on MT6765 SoC Date: Tue, 4 Sep 2018 16:43:44 +0800 Message-ID: <1536050626-21927-1-git-send-email-shun-chih.yu@mediatek.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patchset introduces support for MediaTek Command-Queue DMA controller. MediaTek Command-Queue DMA controller (CQDMA) on MT6765 SoC is dedicated to memory-to-memory transfer through queue-based descriptor management. There are only 3 physical channels inside CQDMA, while the driver is extended to support 32 virtual channels for multiple dma users to issue dma requests onto the CQDMA simultaneously. Shun-Chih Yu (2): dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC .../devicetree/bindings/dma/mtk-cqdma.txt | 31 + drivers/dma/mediatek/Kconfig | 12 + drivers/dma/mediatek/Makefile | 1 + drivers/dma/mediatek/mtk-cqdma.c | 952 +++++++++++++++++++++ 4 files changed, 996 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.txt create mode 100644 drivers/dma/mediatek/mtk-cqdma.c