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Date:   Wed, 5 Sep 2018 09:01:53 +0200
From:   Maxime Ripard <maxime.ripard@bootlin.com>
To:     Stephen Boyd <sboyd@kernel.org>
Cc:     Chen-Yu Tsai <wens@csie.org>, Icenowy Zheng <icenowy@aosc.io>,
        linux-sunxi@googlegroups.com, linux-clk@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] clk: sunxi-ng: sun50i: h6: Add 2x fixed post-divider to
 MMC module clocks
Message-ID: <20180905070153.a5ba6razlhdwdjde@flea>
References: <20180820134013.16527-1-icenowy@aosc.io>
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On Mon, Aug 27, 2018 at 01:23:54PM -0700, Stephen Boyd wrote:
> Quoting Icenowy Zheng (2018-08-20 06:40:13)
> > On the H6, the MMC module clocks are fixed in the new timing mode,
> > i.e. they do not have a bit to select the mode. These clocks have
> > a 2x divider somewhere between the clock and the MMC module.
> >=20
> > To be consistent with other SoCs supporting the new timing mode,
> > we model the 2x divider as a fixed post-divider on the MMC module
> > clocks.
> >=20
> > This patch adds the post-dividers to the MMC clocks, following the
> > approach on A64.
> >=20
> > Fixes: 542353ea ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
>=20
> This commit doesn't exist. Did you mean:
>=20
> 524353ea48
>=20
> instead?

I changed it. Please also use 12-characters commit IDs, as recommended
in the kernel documentation.

Maxime

--=20
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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