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[209.132.180.67]) by mx.google.com with ESMTP id w3-v6si4457594ply.370.2018.09.06.02.25.39; Thu, 06 Sep 2018 02:25:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=a4pksL9J; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728357AbeIFN7C (ORCPT + 99 others); Thu, 6 Sep 2018 09:59:02 -0400 Received: from mail-qt0-f193.google.com ([209.85.216.193]:46270 "EHLO mail-qt0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727951AbeIFN7B (ORCPT ); Thu, 6 Sep 2018 09:59:01 -0400 Received: by mail-qt0-f193.google.com with SMTP id d4-v6so11391931qtn.13 for ; Thu, 06 Sep 2018 02:24:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=xmCte+4fgUFOjCLbLVehYz54TysgyiRsjGxk0i6p7AE=; b=a4pksL9JyCDop+zQjB23kQdb5h0wLPh1HYEYRB5telC1KNqQ5HVGdzkDpUDro1KfSC MRv59M0V4EUqlSx6SUOeMzmg0QPuzU04LqSI7fKVnNDF3DoDsASL2N8ppIu7+KR2SeUi +iKZVTv7RWNOJPjrN8D2eLc8e8aEdaVLT+jKc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=xmCte+4fgUFOjCLbLVehYz54TysgyiRsjGxk0i6p7AE=; b=ZmlXeDCblEATGd9gOHzIkbkhTbVY3RZZB6iVdt3kRsU1as3J114FLQZqXsMaXKVpMg YYtFTKdOHPFvLhc2fBE7rLCC6sRy+rPaJf4hb1Z3OsMcok0GwZRTvnDKsjqcfxwwTPa0 TO2TMPzQa57Bhge7+nk/w2bhqjMfEJ1QfZG5gg3C/L7awT+3DTn4UvoUui537aiQlaXl kPFD58ANAlWT5MjwPQKzB3XN7BRC8tz2mE6N0HTVQVtPo4tGZ4vexPPJPZsjsgnyIz5+ C2+EsH2ewVIJJ9GUi7qh5/3qbOrIiATT2O7w88EELsSWmdmDOBlfqz+0QmInrnTHP7bH g0Tg== X-Gm-Message-State: APzg51DFd+YMcmkQEl446DFxgT+ISNXHxRGp1SnI+079NnIrQLQZjxbk 9hCuHv3aj1okWUWNjyO/h2oEsdDe/63/248XtrEP5w== X-Received: by 2002:ac8:6790:: with SMTP id b16-v6mr1328293qtp.66.1536225867577; Thu, 06 Sep 2018 02:24:27 -0700 (PDT) MIME-Version: 1.0 References: <882739b10bd0a3b655baef9b7ee1958680aa0b04.1535462942.git.amit.kucheria@linaro.org> <20180903200255.GL3456@tuxbook-pro> In-Reply-To: <20180903200255.GL3456@tuxbook-pro> From: Amit Kucheria Date: Thu, 6 Sep 2018 14:54:16 +0530 Message-ID: Subject: Re: [PATCH v2 01/11] arm/arm64: dts: msm8974/msm8916: thermal: Split address space into two To: Bjorn Andersson Cc: Linux Kernel Mailing List , Rajendra Nayak , linux-arm-msm , Eduardo Valentin , smohanad@codeaurora.org, Andy Gross , Doug Anderson , mka@chromium.org, David Brown , Rob Herring , Mark Rutland , Zhang Rui , Daniel Lezcano , "open list:ARM/QUALCOMM SUPPORT" , DTML , Linux PM list Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Sep 4, 2018 at 1:29 AM Bjorn Andersson wrote: > > On Tue 28 Aug 06:38 PDT 2018, Amit Kucheria wrote: > > > We've earlier added support to split the register address space into TM > > and SROT regions. > > > > Split up the regmap address space into two for the remaining platforms > > that have a similar register layout and make corresponding changes to > > the get_temp_common() function used by these platforms. > > > > Since tsens-common.c/init_common() currently only registers one address > > space, the order is important (TM before SROT). This is OK since the > > code doesn't really use the SROT functionality yet. > > > > Having a single patch touching both code and dts will cause merge issues > as this patch travel upstream. Even more arm-soc expects arm and arm64 > dts changes to come in different pull requests. > Please split it so that the three pieces can be picked up by respective > maintainer. Will do. > > Signed-off-by: Amit Kucheria > > Reviewed-by: Matthias Kaehlcke > > --- > > arch/arm/boot/dts/qcom-msm8974.dtsi | 5 +++-- > > arch/arm64/boot/dts/qcom/msm8916.dtsi | 5 +++-- > > drivers/thermal/qcom/tsens-common.c | 5 +++-- > > 3 files changed, 9 insertions(+), 6 deletions(-) > > > > diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi > > index d9019a49b292..56dbbf788d15 100644 > > --- a/arch/arm/boot/dts/qcom-msm8974.dtsi > > +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi > > @@ -427,9 +427,10 @@ > > }; > > }; > > > > - tsens: thermal-sensor@fc4a8000 { > > + tsens: thermal-sensor@fc4a9000 { > > compatible = "qcom,msm8974-tsens"; > > - reg = <0xfc4a8000 0x2000>; > > + reg = <0xfc4a9000 0x1000>, /* TM */ > > + <0xfc4a8000 0x1000>; /* SROT */ > > nvmem-cells = <&tsens_calib>, <&tsens_backup>; > > nvmem-cell-names = "calib", "calib_backup"; > > #thermal-sensor-cells = <1>; > > diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi > > index 7b32b8990d62..6a277fce3333 100644 > > --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi > > +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi > > @@ -761,9 +761,10 @@ > > }; > > }; > > > > - tsens: thermal-sensor@4a8000 { > > + tsens: thermal-sensor@4a9000 { > > compatible = "qcom,msm8916-tsens"; > > - reg = <0x4a8000 0x2000>; > > + reg = <0x4a9000 0x1000>, /* TM */ > > + <0x4a8000 0x1000>; /* SROT */ > > nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; > > nvmem-cell-names = "calib", "calib_sel"; > > #thermal-sensor-cells = <1>; > > diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c > > index 6207d8d92351..478739543bbc 100644 > > --- a/drivers/thermal/qcom/tsens-common.c > > +++ b/drivers/thermal/qcom/tsens-common.c > > @@ -21,7 +21,7 @@ > > #include > > #include "tsens.h" > > > > -#define S0_ST_ADDR 0x1030 > > +#define STATUS_OFFSET 0x30 > > #define SN_ADDR_OFFSET 0x4 > > #define SN_ST_TEMP_MASK 0x3ff > > #define CAL_DEGC_PT1 30 > > @@ -107,8 +107,9 @@ int get_temp_common(struct tsens_device *tmdev, int id, int *temp) > > unsigned int status_reg; > > int last_temp = 0, ret; > > > > - status_reg = S0_ST_ADDR + s->hw_id * SN_ADDR_OFFSET; > > + status_reg = tmdev->tm_offset + STATUS_OFFSET + s->hw_id * SN_ADDR_OFFSET; > > Wasn't this change part of the previous set that introduced the > tm_offset? If not how did we handle the fact that tmdev->map is already > indented 0x1000 bytes? It was a similar change 5b1283984fa3 ("thermal: tsens: Add support to split up register address space into two") for the get_temp_8996() function. This patch converts over the remaining users. > Both changes looks good, but I'm worries about the order of things. We're OK.