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From:   Arnd Bergmann <arnd@arndb.de>
Date:   Thu, 6 Sep 2018 15:03:16 +0200
Message-ID: <CAK8P3a0qRKEfdyQ5V0JcukTG+e0vSLycoBkC4YxRM_os9_jUcQ@mail.gmail.com>
Subject: Re: [PATCH V3 22/26] dt-bindings: interrupt-controller: C-SKY SMP intc
To:     Guo Ren <ren_guo@c-sky.com>
Cc:     Rob Herring <robh@kernel.org>,
        linux-arch <linux-arch@vger.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        Daniel Lezcano <daniel.lezcano@linaro.org>,
        Jason Cooper <jason@lakedaemon.net>,
        c-sky_gcc_upstream@c-sky.com, gnu-csky@mentor.com,
        Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
        wbx@uclibc-ng.org, Greentime Hu <green.hu@gmail.com>
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On Thu, Sep 6, 2018 at 4:23 AM Guo Ren <ren_guo@c-sky.com> wrote:
> On Wed, Sep 05, 2018 at 07:45:12PM -0500, Rob Herring wrote:
> > On Wed, Sep 5, 2018 at 7:09 AM Guo Ren <ren_guo@c-sky.com> wrote:
> > > +
> > > +C-SKY Multi-processors Interrupt Controller is designed for ck807/ck810/ck860
> > > +SMP soc, and it also could be used in non-SMP system.
> >
> > How is it accessed? No mmio registers?
> Mmio reg base is got from cpu-coprocessor register and I'll detail
> it here in next version patch.
>
> csky_mpintc_init(struct device_node *node, struct device_node *parent)
> {
>         ...
>         INTCG_base = ioremap(mfcr("cr<31, 14>"), INTC_SIZE);

It that reliable? I remember a similar situation with some registers on ARM
that are usually identified through a special CPU register, but in some
cases the SoC integrator put the wrong address in there, so we need to
look up the address in DT anyway.

      Arnd