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[209.132.180.67]) by mx.google.com with ESMTP id q5-v6si5566454pgv.692.2018.09.06.13.21.46; Thu, 06 Sep 2018 13:22:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZAME6Hmj; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729878AbeIFSWD (ORCPT + 99 others); Thu, 6 Sep 2018 14:22:03 -0400 Received: from mail-it0-f68.google.com ([209.85.214.68]:55958 "EHLO mail-it0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729708AbeIFSWC (ORCPT ); Thu, 6 Sep 2018 14:22:02 -0400 Received: by mail-it0-f68.google.com with SMTP id d10-v6so14785617itj.5 for ; Thu, 06 Sep 2018 06:46:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=OMIoBcyCnnsiRKrbYO+gBBx66uwywt8vjOE+4okCjUU=; b=ZAME6HmjjFEx/3AkJwjhOqiWmFpgXSTNyCPi8TtSj7NpspIZoR0CqkCLrzPDE4+B0s juJYks+mLp0fuFXFNFcTl0gbQnqfkIR7+81/GxzWX2zNOX0IEyzayup9ICK53zMiJzVD KgN44TtLvdUG4HLDD3l5NxBRzMQS/cWci1oYk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=OMIoBcyCnnsiRKrbYO+gBBx66uwywt8vjOE+4okCjUU=; b=EkZb9FQVe+2Edl64xle8wy1WYPm0cxWTOSNVh5ldhHuLVsXO1kfrYerxtxQk+bpDr/ a3xQ5MnwtKJbeC0RDOSityFA1J3VJEsCh8fN6ZNz9p3yjcLhM1FnfeLNJQlPiRlQFHRW KAErR7FOZp9Pmm3mzVmJIMxN3hveE4dtnlQJQPsMcdg5bcuMYBlZJ+B0bmfSk1PAFTkg 8EohOc78e/OlVyWSvjENU1EtRl23PkUs45+P0L6fYf+kethd/i9V1h8I+Un6/31qYswP qx0MudZIq8ukqAYvwSOklSkv91ZaFmLqE+FjQrVj0aY2xHJaB+51owpJzuV8K8Im954p vQUw== X-Gm-Message-State: APzg51CLEoVbr0V0wxUMMZR0JKeiELj+NL2/tZbXErhvpBXQGjqUaPi0 XTTukJ+Qh2iSltF+nH+XbYtyE5QB5JEp/pAZEgDHPA== X-Received: by 2002:a24:6b0d:: with SMTP id v13-v6mr2801025itc.16.1536241584783; Thu, 06 Sep 2018 06:46:24 -0700 (PDT) MIME-Version: 1.0 References: <20180905104120.17252-1-ckeepax@opensource.cirrus.com> In-Reply-To: <20180905104120.17252-1-ckeepax@opensource.cirrus.com> From: Linus Walleij Date: Thu, 6 Sep 2018 15:46:12 +0200 Message-ID: Subject: Re: [PATCH 1/5] mfd: lochnagar: Add support for the Cirrus Logic Lochnagar To: Charles Keepax Cc: Lee Jones , Michael Turquette , Stephen Boyd , Mark Brown , Rob Herring , Mark Rutland , Liam Girdwood , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "linux-kernel@vger.kernel.org" , patches@opensource.cirrus.com Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Sep 5, 2018 at 12:41 PM Charles Keepax wrote: > From: Charles Keepax > > Lochnagar is an evaluation and development board for Cirrus > Logic Smart CODEC and Amp devices. It allows the connection of > most Cirrus Logic devices on mini-cards, as well as allowing > connection of various application processor systems to provide a > full evaluation platform. Audio system topology, clocking and > power can all be controlled through the Lochnagar, allowing the > device under test to be used in a variety of possible use cases. > > As the Lochnagar is a fairly complex device this MFD driver > allows the drivers for the various features to be bound > in. Initially clocking, regulator and pinctrl will be added as > these are necessary to configure the system. But in time at least > audio and voltage/current monitoring will also be added. > > Signed-off-by: Charles Keepax It's a bit confusing, maybe you can clear it up: it appears to be an I2C device, so when you say this is a "development board" is there something like a board controller that is accessed over I2C and this is what the driver really probes to, not the board per se? I guess jamming this card into the I2C slot of any other system (would work fine with a 96Boards LS connector as it seems, actually) also involves connecting some I2S or similar on the side for high-datarate traffic? This driver seems to only concern itself with the I2C board controller per se, not the board is that right? Yours, Linus Walleij