Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
From:   Sasha Levin <Alexander.Levin@microsoft.com>
To:     "stable@vger.kernel.org" <stable@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
CC:     Rex Zhu <rex.zhu@amd.com>, Rex Zhu <Rex.Zhu@amd.com>,
        Alex Deucher <alexander.deucher@amd.com>,
        Sasha Levin <Alexander.Levin@microsoft.com>
Subject: [PATCH AUTOSEL 4.18 79/88] drm/amd/pp: Set Max clock level to display
 by default
Thread-Topic: [PATCH AUTOSEL 4.18 79/88] drm/amd/pp: Set Max clock level to
 display by default
Thread-Index: AQHURkLcRRSKg/5WIk+/vGWjHBHe9g==
Date:   Fri, 7 Sep 2018 00:36:47 +0000
Message-ID: <20180907003547.57567-79-alexander.levin@microsoft.com>
References: <20180907003547.57567-1-alexander.levin@microsoft.com>
In-Reply-To: <20180907003547.57567-1-alexander.levin@microsoft.com>
Accept-Language: en-US
Content-Language: en-US
received-spf: None (protection.outlook.com: microsoft.com does not designate
 permitted sender hosts)
spamdiagnosticoutput: 1:99
spamdiagnosticmetadata: NSPM
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
MIME-Version: 1.0
X-MS-Exchange-CrossTenant-Network-Message-Id: 9c9e5c0d-6de0-4be9-3c53-08d6145a1c6b
X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Sep 2018 00:36:47.7577
 (UTC)
X-MS-Exchange-CrossTenant-fromentityheader: Hosted
X-MS-Exchange-CrossTenant-id: 72f988bf-86f1-41af-91ab-2d7cd011db47
X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR21MB0839
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

From: Rex Zhu <rex.zhu@amd.com>

[ Upstream commit 97e8f102f5a9123d30258e196c6c1ea29cf52e83 ]

avoid the error in dmesg:
[drm:dm_pp_get_static_clocks]
*ERROR* DM_PPLIB: invalid powerlevel state: 0!

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
---
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/dr=
m/amd/powerplay/amd_powerplay.c
index d567be49c31b..b487774d8041 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -1020,7 +1020,7 @@ static int pp_get_display_power_level(void *handle,
 static int pp_get_current_clocks(void *handle,
 		struct amd_pp_clock_info *clocks)
 {
-	struct amd_pp_simple_clock_info simple_clocks;
+	struct amd_pp_simple_clock_info simple_clocks =3D { 0 };
 	struct pp_clock_info hw_clocks;
 	struct pp_hwmgr *hwmgr =3D handle;
 	int ret =3D 0;
@@ -1056,7 +1056,10 @@ static int pp_get_current_clocks(void *handle,
 	clocks->max_engine_clock_in_sr =3D hw_clocks.max_eng_clk;
 	clocks->min_engine_clock_in_sr =3D hw_clocks.min_eng_clk;
=20
-	clocks->max_clocks_state =3D simple_clocks.level;
+	if (simple_clocks.level =3D=3D 0)
+		clocks->max_clocks_state =3D PP_DAL_POWERLEVEL_7;
+	else
+		clocks->max_clocks_state =3D simple_clocks.level;
=20
 	if (0 =3D=3D phm_get_current_shallow_sleep_clocks(hwmgr, &hwmgr->current_=
ps->hardware, &hw_clocks)) {
 		clocks->max_engine_clock_in_sr =3D hw_clocks.max_eng_clk;
@@ -1159,6 +1162,8 @@ static int pp_get_display_mode_validation_clocks(void=
 *handle,
 	if (!hwmgr || !hwmgr->pm_en ||!clocks)
 		return -EINVAL;
=20
+	clocks->level =3D PP_DAL_POWERLEVEL_7;
+
 	mutex_lock(&hwmgr->smu_lock);
=20
 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_Platform=
Caps_DynamicPatchPowerState))
--=20
2.17.1