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Date:   Fri, 7 Sep 2018 10:21:22 +0200
From:   Maxime Ripard <maxime.ripard@bootlin.com>
To:     Jagan Teki <jagan@amarulasolutions.com>
Cc:     Icenowy Zheng <icenowy@aosc.io>, Chen-Yu Tsai <wens@csie.org>,
        Jernej Skrabec <jernej.skrabec@siol.net>,
        dri-devel <dri-devel@lists.freedesktop.org>,
        devicetree <devicetree@vger.kernel.org>,
        linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
        linux-kernel <linux-kernel@vger.kernel.org>,
        linux-clk <linux-clk@vger.kernel.org>,
        linux-sunxi <linux-sunxi@googlegroups.com>
Subject: Re: [PATCH v4 08/11] arm64: dts: allwinner: a64: Add display pipeline
Message-ID: <20180907082122.bcylf2jpf6eq6dgq@flea>
References: <20180904044053.15425-1-icenowy@aosc.io>
 <20180904044053.15425-9-icenowy@aosc.io>
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On Fri, Sep 07, 2018 at 09:43:29AM +0530, Jagan Teki wrote:
> On Wed, Sep 5, 2018 at 1:20 PM, Maxime Ripard <maxime.ripard@bootlin.com>=
 wrote:
> > On Tue, Sep 04, 2018 at 12:40:50PM +0800, Icenowy Zheng wrote:
> >> +             hdmi_phy: hdmi-phy@1ef0000 {
> >> +                     compatible =3D "allwinner,sun8i-h3-hdmi-phy";
> >> +                     reg =3D <0x01ef0000 0x10000>;
> >> +                     clocks =3D <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_D=
DC>,
> >> +                              <&ccu 7>;
> >> +                     clock-names =3D "bus", "mod", "pll-0";
> >> +                     resets =3D <&ccu RST_BUS_HDMI0>;
> >> +                     reset-names =3D "phy";
> >> +                     #phy-cells =3D <0>;
> >> +             };
> >
> > This needs to use the bindings we have for that phy.
>=20
> You mean allwinner,sun50i-a64-hdmi-phy ?

Yes

Maxime

--=20
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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