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[209.132.180.67]) by mx.google.com with ESMTP id f91-v6si10860052plf.376.2018.09.08.04.09.45; Sat, 08 Sep 2018 04:10:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727256AbeIHPxY (ORCPT + 99 others); Sat, 8 Sep 2018 11:53:24 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:38749 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726937AbeIHPxW (ORCPT ); Sat, 8 Sep 2018 11:53:22 -0400 X-UUID: b2d28c2b56c04f9a8f33a3125d827df8-20180908 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 290265857; Sat, 08 Sep 2018 19:07:43 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Sat, 8 Sep 2018 19:07:42 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Sat, 8 Sep 2018 19:07:43 +0800 From: To: , CC: , , , Zhiyong Tao , "Sean Wang" Subject: [PATCH v2 20/22] pintcrl: mediatek: add pull tweaks for I2C related pins on MT8183 Date: Sat, 8 Sep 2018 19:07:36 +0800 Message-ID: <3d957d32b5b0f67548f63ae4ba7176dba9e61faa.1536404280.git.sean.wang@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Zhiyong Tao This patch provides the advanced pull for I2C used pins on MT8183. Signed-off-by: Zhiyong Tao Signed-off-by: Sean Wang --- drivers/pinctrl/mediatek/pinctrl-mt8183.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8183.c b/drivers/pinctrl/mediatek/pinctrl-mt8183.c index bd3f00b..9d5aa27 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8183.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8183.c @@ -397,10 +397,22 @@ static const struct mtk_pin_field_calc mt8183_pin_r0_range[] = { PIN_FIELD_BASE(40, 40, 3, 0x0C0, 0x10, 20, 1), PIN_FIELD_BASE(41, 41, 3, 0x0C0, 0x10, 24, 1), PIN_FIELD_BASE(42, 42, 3, 0x0C0, 0x10, 28, 1), + PIN_FIELD_BASE(48, 48, 3, 0x0F0, 0x10, 18, 1), + PIN_FIELD_BASE(49, 49, 3, 0x0F0, 0x10, 13, 1), + PIN_FIELD_BASE(50, 50, 4, 0x0F0, 0x10, 10, 1), + PIN_FIELD_BASE(51, 51, 4, 0x0F0, 0x10, 5, 1), + PIN_FIELD_BASE(81, 81, 5, 0x0F0, 0x10, 7, 1), + PIN_FIELD_BASE(82, 82, 5, 0x0F0, 0x10, 5, 1), + PIN_FIELD_BASE(83, 83, 5, 0x0F0, 0x10, 15, 1), + PIN_FIELD_BASE(84, 84, 5, 0x0F0, 0x10, 17, 1), PIN_FIELD_BASE(91, 91, 6, 0x0C0, 0x10, 0, 1), PIN_FIELD_BASE(92, 92, 6, 0x0C0, 0x10, 4, 1), PIN_FIELD_BASE(93, 93, 6, 0x0C0, 0x10, 8, 1), PIN_FIELD_BASE(94, 94, 6, 0x0C0, 0x10, 12, 1), + PIN_FIELD_BASE(103, 103, 6, 0x0F0, 0x10, 20, 1), + PIN_FIELD_BASE(104, 104, 6, 0x0F0, 0x10, 10, 1), + PIN_FIELD_BASE(105, 105, 6, 0x0F0, 0x10, 22, 1), + PIN_FIELD_BASE(106, 106, 6, 0x0F0, 0x10, 12, 1), PIN_FIELD_BASE(122, 122, 8, 0x0C0, 0x10, 0, 1), PIN_FIELD_BASE(123, 123, 8, 0x0C0, 0x10, 4, 1), PIN_FIELD_BASE(124, 124, 8, 0x0C0, 0x10, 8, 1), @@ -430,10 +442,22 @@ static const struct mtk_pin_field_calc mt8183_pin_r1_range[] = { PIN_FIELD_BASE(40, 40, 3, 0x0C0, 0x10, 21, 1), PIN_FIELD_BASE(41, 41, 3, 0x0C0, 0x10, 25, 1), PIN_FIELD_BASE(42, 42, 3, 0x0C0, 0x10, 29, 1), + PIN_FIELD_BASE(48, 48, 3, 0x0F0, 0x10, 19, 1), + PIN_FIELD_BASE(49, 49, 3, 0x0F0, 0x10, 14, 1), + PIN_FIELD_BASE(50, 50, 4, 0x0F0, 0x10, 11, 1), + PIN_FIELD_BASE(51, 51, 4, 0x0F0, 0x10, 6, 1), + PIN_FIELD_BASE(81, 81, 5, 0x0F0, 0x10, 8, 1), + PIN_FIELD_BASE(82, 82, 5, 0x0F0, 0x10, 6, 1), + PIN_FIELD_BASE(83, 83, 5, 0x0F0, 0x10, 16, 1), + PIN_FIELD_BASE(84, 84, 5, 0x0F0, 0x10, 18, 1), PIN_FIELD_BASE(91, 91, 6, 0x0C0, 0x10, 1, 1), PIN_FIELD_BASE(92, 92, 6, 0x0C0, 0x10, 5, 1), PIN_FIELD_BASE(93, 93, 6, 0x0C0, 0x10, 9, 1), PIN_FIELD_BASE(94, 94, 6, 0x0C0, 0x10, 13, 1), + PIN_FIELD_BASE(103, 103, 6, 0x0F0, 0x10, 21, 1), + PIN_FIELD_BASE(104, 104, 6, 0x0F0, 0x10, 11, 1), + PIN_FIELD_BASE(105, 105, 6, 0x0F0, 0x10, 23, 1), + PIN_FIELD_BASE(106, 106, 6, 0x0F0, 0x10, 13, 1), PIN_FIELD_BASE(122, 122, 8, 0x0C0, 0x10, 1, 1), PIN_FIELD_BASE(123, 123, 8, 0x0C0, 0x10, 5, 1), PIN_FIELD_BASE(124, 124, 8, 0x0C0, 0x10, 9, 1), -- 2.7.4