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Date:   Mon, 10 Sep 2018 04:27:09 -0700
From:   Christoph Hellwig <hch@infradead.org>
To:     Atish Patra <atish.patra@wdc.com>
Cc:     palmer@sifive.com, linux-riscv@lists.infradead.org,
        hch@infradead.org, anup@brainfault.org, mark.rutland@arm.com,
        Damien.LeMoal@wdc.com, jason@lakedaemon.net,
        ard.biesheuvel@linaro.org, marc.zyngier@arm.com,
        gregkh@linuxfoundation.org, dmitriy@oss-tech.org,
        linux-kernel@vger.kernel.org, jeremy.linton@arm.com,
        catalin.marinas@arm.com, tglx@linutronix.de
Subject: Re: [PATCH v3 09/12] RISC-V: User WRITE_ONCE instead of direct access
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On Thu, Sep 06, 2018 at 01:05:32AM -0700, Atish Patra wrote:
> The secondary harts spin on couple of per cpu variables until both of
> these are non-zero so it's not necessary to have any ordering here.
> However, WRITE_ONCE should be used to avoid tearing.

We normally pair WRITE_ONCE with READ_ONCE.  But it seems like the
reader side is in assembly code, so this should be ok:

Reviewed-by: Christoph Hellwig <hch@lst.de>